Circuitry and method for multi-bit correction

ABSTRACT

A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell.

FIELD

The present invention relates to error correction and error detection,and, in particular, to an apparatus and method for correction of errorsof memories with memory cells with more than two states.

BACKGROUND

Error correction and error detection techniques play an important role.Not only in the field of computer networks and data transmission overwired and wireless networks but also in the field of protection ofmemory content, error correction and error detection techniques arewidely employed.

While conventional memories comprise binary memory cells, in the lastyears, ternary memory cells, which can take on three different valueshave become increasingly important.

It would be highly beneficial if improved concepts for correction oferrors in memories with memory cells with more than two states would beprovided.

SUMMARY

According to an embodiment, a circuitry is provided. The circuitrycomprises a memory comprising a plurality of memory cells, wherein oneor more of the plurality of memory cells of the memory are each adaptedto take on one of at least three different states. The circuitry furthercomprises a first subcircuit BT configured to generate a plurality ofoutput values, based on a sequence of binary values, wherein a nonemptysubset of the plurality of output values has one of at least threedifferent values of the nonempty subset of output values, and whereinthe first subcircuit BT is configured to store each of the output valuesas a state value in a different one of the one or more memory cellswhich are each adapted to take on one of the at least three differentstates. The circuitry also comprises a second subcircuit LH configuredto read one or more of the state values from at least one of the memorycells which are adapted to take on one of the at least three differentstates, wherein each of the one or more state values has one of at theat least three different basic values, and wherein the second subcircuitLH is furthermore configured to determine binary auxiliary read valuesbased on the one or more state values. Lastly, the circuitry comprisesan encoder configured to generate one or more binary check bits based onat least some values of the sequence of binary values, wherein anerror-correcting code comprises a plurality of codewords, and whereinthe encoder is configured to generate the one or more binary check bitsso that the binary auxiliary read values and the one or more binarycheck bits together form one of the codewords of the error-correctingcode, when the binary auxiliary read values y₁′, . . . , y_(k)′ and theone or more binary check bits c₁, . . . , c_(l) are error-free. Theencoder is configured to store each of the generated one or more checkbits in one or more of the memory cells of the memory, such that each ofthe one or more check bits is stored in a different one of the memorycells of the memory, wherein each one of the memory cells in which acheck bit is stored is adapted to take on one of at least two differentstates.

Moreover, a circuitry according to another embodiment is provided. Thecircuitry comprises a memory comprising a plurality of memory cells,wherein one or more of the plurality of memory cells of the memory areternary memory cells each being adapted to take on one of threedifferent states. The circuitry further comprises a first subcircuit BTconfigured to generate a plurality of output values, based on a sequenceof binary values, wherein a nonempty subset of the plurality of outputvalues has one of three different basic values, wherein the firstsubcircuit is configured to store each of the output values of thenonempty subset of output values as a state value in a different one ofthe one or more ternary memory cells which are each adapted to take onone of the three different states, and the remaining output values inmemory cells configured to store at least two different values. Thecircuitry also comprises a second subcircuit LH configured to read oneor more of the state values from the memory cells, wherein the secondsubcircuit LH is furthermore configured to determine binary auxiliaryread values based on the one or more state values. The circuitry alsocomprises an encoder configured to generate one or more binary checkbits based on at least some values of the sequence of binary values,wherein an error-correcting code comprises a plurality of codewords, andwherein the encoder is configured to generate the one or more binarycheck bits so that the binary auxiliary read values and the one or morebinary check bits together form one of the codewords of theerror-correcting code, when the binary auxiliary read values y₁′, . . ., y_(k)′ and the one or more binary check bits c₁, . . . , c_(l) areerror-free. The encoder is configured to store each of the generated oneor more check bits in one or more of the memory cells of the memory,such that each of the one or more check bits is stored in a differentone of the memory cells of the memory, wherein each one of the memorycells in which a check bit is stored is adapted to take on one of atleast two different states. The circuitry further comprises a correctorCor, a combinational circuit Vkn, and a third subcircuit BB, wherein thesecond subcircuit LH is configured to feed the binary auxiliary readvalues into the corrector Cor and into the combinational circuit Vkn.The corrector Cor is configured to read the one or more check bits fromone or more of the memory cells of the memory, wherein the corrector Coris configured to generate the error correction bits based on the binaryauxiliary read values and the one or more check bits, and wherein thecorrector Cor is configured to feed the error correction bits into thecombinational circuit Vkn. The combinational circuit Vkn is configuredto conduct error correction on the binary auxiliary read values based onthe error correction bits to obtain binary auxiliary error-free, e.g.corrected, read values, and the third subcircuit BB is configured totransform of the binary auxiliary error-free read values into binarycorrected data bits.

Furthermore, a circuitry according to another embodiment is provided.The circuitry is configured to store sequences of binary values x₁, . .. , x_(n) in a memory Sp comprising memory cells, wherein n≧3, whereineach of the memory cells of the memory is either adapted to take on oneof three state values or to take on one of two state values, and whereinat least one of the memory cells of the memory is adapted to take on oneof three state values. The circuitry comprises a first subcircuit BThaving n binary inputs and M outputs, wherein the first subcircuit BT isadapted to transform n binary input values x₁, . . . , x_(n) into Moutput values z₁, . . . , z_(m), z_(m+1), . . . , z_(M)=BT(x₁, . . . ,x_(n)), wherein 2≦m≦M, wherein M<n, and wherein n≧4, wherein each of theoutput values z₁, . . . , z_(m) has one of three different valuesdepending on the binary input values. Each of the output values z_(m+1),. . . , z_(M) has one of at most two different values depending on thebinary input values, wherein the first subcircuit BT has M outputs whichare connected with M data inputs of the memory Sp, wherein, when writinginto the memory Sp, the output values z₁, . . . , z_(m) of the firstsubcircuit BT are stored into the memory cells of the memory, which areadapted to take on one of three states, and wherein the output valuesz_(m+1), . . . , z_(M) are stored in memory cells which are adapted totake on one of at least two state values. The circuitry furthercomprises a second subcircuit LH for determining binary auxiliary readvalues y₁′, . . . , y_(k)′=LH(z₁′, . . . , z_(m)′, z_(m+1)′, . . . ,z_(M)′), wherein the second subcircuit LH has M inputs and k outputs,wherein, when reading from the memory, m first inputs of the inputs ofthe second subcircuit LH are connected to the data outputs of the memorycells of memory Sp, into which, when writing, the ternary values z₁, . .. , z_(m) are written, and from which, when reading, the possiblyerroneous ternary values z₁′, . . . , z_(m)′ are read out. Further, M−minputs of the second subcircuit LH are connected to the data outputs ofthe memory cells into which, when writing, the values z_(m), . . . ,z_(M) are written, and from which, when reading, the possible erroneousvalues z_(m+1)′, . . . , z_(M)′ are read out, and wherein the secondsubcircuit LH outputs k possibly erroneous binary auxiliary read valuesy₁′, . . . , y_(k)′ with k≧m+M at its k outputs. The circuitry alsocomprises an encoder Cod with n binary inputs and l binary outputs fordetermining l binary check bits c₁, . . . , c_(l) from the n binaryinput values x₁, . . . , x_(n) with c₁, . . . , c_(l)=Cod(x₁, . . . ,x_(n)), wherein at n binary inputs of the encoder Cod, the binary inputvalues x₁, . . . , x_(n) are applied, and at l binary outputs of theencoder, binary check bits c₁, . . . , c_(l) determined by the binaryinput values x₁, . . . , x_(n) are output. The encoder is configured, sothat it determines the check bits c₁, . . . c_(l) from the binary inputvalues x₁, . . . , x_(n) so that bits y₁, . . . , y_(k), c₁, . . . ,c_(l) form a codeword of an error-correcting code C of the length k+lwith k data bits and l check bits, where y₁, . . . , y_(k) are the kbinary error free auxiliary read values.

According to another embodiment, a method is provided. The methodcomprises generating a plurality of output values based on a sequence ofbinary values, wherein each of the plurality of output values has one ofat least three different basic values. The method further comprisesstoring each of the output values as a state value in a different one ofone or more memory cells of a plurality of memory cells of a memory,wherein the one or more memory cells, in which the output values arestored, are each adapted to take on one of at least three differentstates. The method also comprises reading one or more of the statevalues from at least one of the memory cells which are adapted to takeon one of the at least three different states, wherein each of the oneor more state values has one of the at least three different basicvalues, wherein the binary auxiliary read values are determined based onthe one or more state values. The method continues by generating one ormore binary check bits so that the binary auxiliary read values and theone or more binary check bits together form one of the codewords of theerror-correcting code, when the binary auxiliary read values y₁′, . . ., y_(k)′ and the one or more binary check bits c₁, . . . , c_(l) areerror-free, and storing each of the generated one or more check bits inone or more of the memory cells of the memory, such that each of the oneor more check bits is stored in a different one of the memory cells ofthe memory, wherein each one of the memory cells in which a check bit isstored is adapted to take on one of at least two different states.

Before embodiments of the present invention are described in detailusing the accompanying figures, it is to be pointed out that the same orfunctionally equal elements are given the same reference numbers in thefigures and that a repeated description for elements provided with thesame reference numbers is omitted. Hence, descriptions provided forelements having the same reference numbers are mutually exchangeable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a illustrates circuitry for error correction according to anembodiment.

FIG. 1 b illustrates circuitry for error correction according to anotherembodiment.

FIG. 1 c illustrates circuitry for error correction according to afurther embodiment.

FIG. 1 d illustrates circuitry for error correction according to afurther embodiment.

FIG. 1 e illustrates circuitry for error correction, moreover providingadditional error detection, according to an embodiment.

FIG. 1 f depicts circuitry having a binary partial memory according toan embodiment.

FIG. 1 g illustrates an implementation for additional error detection ofaddress errors according to an embodiment.

FIG. 1 h illustrates circuitry according to an embodiment, wherein databits are stored in memory cells of a ternary memory circuitry,

FIG. 1 i illustrates ternary memory circuitry according to anembodiment,

FIG. 1 j illustrates ternary memory circuitry according to anotherembodiment,

FIG. 1 k illustrates ternary memory circuitry according to a furtherembodiment,

FIG. 2 illustrates an implementation of a coder according to anembodiment.

FIGS. 3 a-3 c depict implementations of subcircuits for thetransformation of binary input values into ternary state valuesaccording to an embodiment.

FIG. 4 depicts an implementation of a subcircuit for the transformationof ternary state values into binary auxiliary read values according toan embodiment.

FIG. 5 a illustrates an implementation of a coder according to anembodiment.

FIG. 5 b depicts an implementation of a coder for a linearerror-correcting code according to an embodiment.

FIG. 5 c illustrates an implementation of a coder using address bitsaccording to an embodiment.

FIG. 5 d depicts an implementation of a coder for a linearerror-correcting code using the parity of address bits according to anembodiment.

FIG. 5 e shows an implementation of a coder for a linear correcting codeusing all address bits according to an embodiment.

FIG. 6 a illustrates an implementation of a corrector according to anembodiment.

FIG. 6 b shows an implementation of a corrector using address bitsaccording to an embodiment.

FIG. 7 a depicts an implementation of the transformation of the binaryauxiliary read values into binary output values according to anembodiment.

FIG. 7 b shows a further implementation of a transformation of thebinary auxiliary read values into binary output values according to anembodiment.

FIG. 7 c is a further implementation of a transformation of the binaryauxiliary read values into binary output values according to anembodiment.

FIG. 8 illustrates a functional block diagram for explaining asubcircuit according to an embodiment.

FIG. 9 a is an example of a subcircuit for forming binary auxiliarywrite values and ternary state values according to an embodiment.

FIG. 9 b illustrates an implementation of a subcircuit for thetransformation of binary input values into ternary state valuesaccording to an embodiment.

FIG. 10 depicts an implementation of an inventive circuit having 8binary data bits for forming ternary state values and for realizing acoder using auxiliary write values according to an embodiment.

FIG. 11 is an example of a decoder circuit of a linear code according toprior art.

FIG. 12 is an example of an error detection circuit according to priorart.

FIG. 13 is an example of a common realization of an error detectioncircuit and a corrector according to prior art.

DETAILED DESCRIPTION

FIG. 1 a illustrates a circuitry according to an embodiment.

The circuitry comprises a memory Sp 13 comprising a plurality of memorycells, wherein one or more of the plurality of memory cells of thememory are each adapted to take on one of at least three differentstates.

Thus, at least one of the memory cells of the memory is adapted to takeon one of at least three different states. For example, a ternary memorycell is adapted to take on one of exactly three different states. (e.g.the state may represent exactly one of the values 0, 1 or 2). Instead ofa ternary memory cell, the memory may comprise at least one multi-valuedmemory cell, wherein such a multi-valued memory cell may be adapted totake on one of four or more different states (e.g. the state mayrepresent exactly one of the values 0, 1, 2 or 3). The memory comprisesat least one memory cell which is adapted to take on one of at leastthree different states (e.g. a ternary memory cell or a multi-valuedmemory cell which can take on one of more than three different states).The memory may, however, also comprise memory cells which are adapted totake on one of only two different states, e.g. the memory may alsocomprise one or more binary memory cells. However, at least one of thememory cells of the memory is adapted to take on at least one of threedifferent states. In some of the embodiments, however, all memory cellsof the memory may take on one of at least three different states.

The circuitry of FIG. 1 a comprises a first subcircuit BT 11 configuredto generate a plurality of output values z₁, . . . , z_(M), based on asequence of binary values x₁, . . . , x_(n), wherein each of theplurality of output values z₁, . . . , z_(M) has one of at least threedifferent basic values, (e.g. one value of the basic values 0, 1, 2),wherein the first subcircuit BT 11 is configured to store each of theoutput values z₁, . . . , z_(M) in a different one of the one or morememory cells which are each adapted to take on one of the at least threedifferent states. Each of the output values stored in the memory 13 canbe considered as a state value of the corresponding memory cells. Bythis, the plurality of output values stored in memory represents aplurality of state values.

Furthermore, the circuitry comprises a second subcircuit LH 16configured to read one or more of the state values z₁′, . . . , z_(M)′from at least one of the memory cells, the memory cells being adapted totake on one of the at least three different states, wherein each of theone or more state values z₁′, . . . , z_(M)′ has one of the at leastthree different basic values (e.g. one of the values 0, 1, 2), whereinthe second subcircuit LH 16 is furthermore configured to determinebinary auxiliary read values y₁′, . . . , y_(k)′ based on the one ormore state values z₁′, . . . , z_(M)′.

Moreover, the circuitry comprises an encoder Cod 12 configured togenerate one or more binary check bits c₁, . . . , c_(l) based on atleast some values of the sequence of binary values, wherein anerror-correcting code comprises a plurality of codewords, and whereinthe encoder Cod 12 is configured to generate the one or more binarycheck bits c₁, . . . , c_(l) so that the binary auxiliary read valuesy₁′, . . . , y_(k)′ and the one or more binary check bits c₁, . . . ,c_(l) together form one of the codewords of the error-correcting code,when the binary auxiliary read values y₁′, . . . , y_(k)′ and the one ormore binary check bits c₁, . . . , c_(l) are error-free.

The encoder 12 is configured to store each of the generated one or morecheck bits in one or more of the memory cells of the memory 13, suchthat each of the one or more check bits is stored in a different one ofthe memory cells of the memory, wherein each one of the memory cells inwhich a check bit is stored is adapted to take on one of at least twodifferent states.

Basic values may, for example, be all the values, e.g. all the numbers,of a set of values that, for example, an output value or a state valuecan take on. For example, basic values may be all the numbers that avalue, e.g. an output value, a state value or a value of a sequence cantake on.

If, for example, an output value is a ternary value, then the outputvalue can take on one of three values. For example, the output value cantake on one value of the set of values {0, 1, 2}. Then, the threedifferent basic values are 0, 1 and 2.

If, for example, a value of a sequence of binary values is to bedetermined, then, for example, a value of the sequence can take on onevalue of the set of two numbers, e.g. of the set {0, 1}. Then, the valuecan take on one of two different basic values, and the two differentbasic values are 0 and 1.

In an embodiment, the one or more of the plurality of memory cells ofthe memory, which are each adapted to take on one of at least threedifferent states, may be ternary memory cells. In such an embodiment,the first subcircuit BT 11 may be configured to generate the pluralityof output values such that each of the plurality of output values hasone of exactly three different basic values, wherein the firstsubcircuit is configured to store each of the output values in adifferent one of the ternary memory cells. Moreover, the secondsubcircuit LH 16 may be configured to read the one or more state valuesfrom at least one of the ternary memory cells, wherein each of the oneor more state values has one of exactly three different basic values,and wherein the second subcircuit LH 16 is furthermore configured todetermine binary auxiliary read values based on the one or more statevalues.

FIG. 1 b illustrates circuitry according to another embodiment. Comparedwith the embodiment of FIG. 1 a, the circuitry of the embodiment of FIG.1 b furthermore comprises a corrector Cor 17 and a combinational circuitVkn 18.

The second subcircuit LH 16 is configured to feed the binary auxiliaryread values y₁′, . . . , y_(k)′ into the corrector Cor 17 and into thecombinational circuit Vkn 18.

The corrector Cor 17 is configured to read the one or more check bitsc′=c₁′, . . . , c_(l)′ from one or more of the memory cells Spc₁, . . ., Spc_(l) of the memory, wherein the corrector Cor 17 is configured togenerate the error correction bits e₁, . . . , e_(k) based on the binaryauxiliary read values and the one or more check bits. The corrector Cor17 is configured to feed the error correction bits e₁, . . . , e_(k)into the combinational circuit Vkn 18.

The combinational circuit Vkn 18 is configured to conduct errorcorrection on the binary auxiliary read values y₁′, . . . , y_(k)′ basedon the error correction bits e₁, . . . , e_(k) to obtain binaryauxiliary error-free read values y^(cor).

In an embodiment, the combinational circuit Vkn 18 is configured toconduct error correction such that the binary auxiliary error-free readvalues y^(cor) and the one or more check bits c′=c₁′, . . . , c_(l)′form one of the codewords of the error-correcting code.

FIG. 1 c illustrates circuitry according to a further embodiment.Compared with the embodiment of FIG. 1 b, the circuitry of theembodiment of FIG. 1 c further comprises a third subcircuit BB 19. Thethird subcircuit BB 19 is configured to transform the binary auxiliaryerror-free read values y^(cor) into n binary error-corrected data bitsx^(cor).

FIG. 1 d illustrates circuitry Cir₁ according to a further embodiment.The circuitry Cir₁ may comprise the following subcircuits:

1. A subcircuit BT 11 for the transformation of a sequence of n binaryinput values or data bits x=x₁, . . . , x_(n) into a sequence of Moutput values z=z₁, . . . , z_(m), z_(m+1), . . . , z_(M),z ₁ , . . . z _(m) ,z _(m+1) . . . ,z _(M) =BT(x ₁ , . . . ,x _(n)),may exist, wherein 2≦m≦M and M<n, n≧3 applies. Here, each of the outputvalues z₁, . . . , z_(m), may take on three different values dependingon the binary values x₁, . . . , x_(n). Depending on the binary valuesx₁, . . . , x_(n), each of the output values z_(m+1), . . . , z_(M) maytake on at most two different values. The subcircuit BT 11 isimplemented so that different sequences of n binary input values aretransformed into different sequences of M binary output values.2. An encoder Cod 12 with n binary inputs and l binary outputs fordetermining l binary check bits c₁, . . . , c_(l) may exist withc ₁ , . . . ,c _(l)=Cod(x ₁ , . . . ,x _(n)),wherein at the n binary inputs, the binary input values x₁, . . . ,x_(n), are applied and at the binary outputs the corresponding checkbits c₁, . . . , c_(l) are output.3. A memory Sp 13 may exist for storing the values z₁, . . . z_(m),z_(m,+1), . . . , z_(M), and c₁, . . . , c_(l), wherein each of thememory cells for storing the values z₁, . . . z_(m) may take on threedifferent values as states, and wherein each of the memory cells forstoring the values z_(m+1), . . . , z_(M), c₁, . . . , c_(l) may take onat least two different values as states. The memory cells which servefor storing the check bits c₁, . . . , c_(l) are designated by Spc₁, . .. , Spc_(l). In FIG. 1 d, the case is illustrated that the memory cellsSpc₁, . . . , Spc_(l) may take on three different states.

For j=1, . . . , l, the j-th output of the encoder 12 which carries thecheckbit c_(j) is connected when writing to the data input of the memorycell Spc_(j) via a subcircuit bt_(j) 14 j with a binary input and aternary output for the transformation of the binary value c_(j) into aternary value c_(j) ^(t)=bt_(j)(c_(j)). Here, the subcircuit bt_(j) 14 jmay transform for example a minimum binary value designated as 0_(bin)into a minimum ternary value designated as 0_(ter), and may transform amaximum binary value designated as 1_(bin) into a maximum ternary valuedesignated as 2_(ter). The subcircuit bt_(j) 14 j may for example alsotransform a minimum binary value designated as 0_(bin) into a maximumternary value designated as 2_(ter) and a maximum binary valuedesignated as 1_(bin) into a minimum ternary value designated as0_(ter).

According to an embodiment, the binary value c_(j), j=1, . . . , l ofthe check bits is each stored as a transformed value c_(j)^(t)=bt_(j)(c_(j)) in a separate memory cell Spc_(j) of the memory Sp13, while the individual data bits x₁, . . . , x_(n) are generally notstored in a separate memory cell of the ternary memory.

By this, the sequence of the n data bits x₁, . . . , x_(n) istransformed into M values z₁, . . . z_(m), z_(m,+1), . . . , z_(M) withM<n by the subcircuit BT, wherein z₁, . . . z_(m) are ternary valueseach stored in a ternary memory cell. Here, for example, three binaryvalues x_(i1), x_(i2), x_(i3) of the data bits are transformed into twoternary values z_(i1), z_(i2) by the subcircuit BT 11, so that then theinformation of three data bits may be stored in two ternary memory cellsas will be described in more detail later.

4. A subcircuit LH 16 may exist for the transformation of the possiblyerroneous state values z₁′, . . . , z_(M)′, which are read out of thememory Sp 13 into k binary auxiliary read valuesy ₁ ′, . . . ,y _(k) ′=LH(z ₁ ′, . . . ,z _(M)′),wherein the subcircuit LH 16 is configured so that different sequencesof M state values, which are read out of the memory, are assigned todifferent sequences of k binary auxiliary read values, wherein to eachternary state component z_(i)′, i=1, . . . , m at least two binaryauxiliary read values are assigned, and wherein to each binary statecomponent z_(j)′, j= m+1, . . . , M, at least one binary auxiliary readvalue is assigned, and wherein k>M applies.

As already indicated, at least two binary auxiliary read values areassigned to one ternary value z_(i)′, 1≦i≦m.

If, for example, a pair y_(i1), y_(i2) of auxiliary read values isassigned to the 3-value state component z_(i), then this pair of binaryauxiliary read values only takes on three of four basically possiblebinary values.

The encoder 12 is implemented so that it determines check bits c₁, . . ., c_(l) so that c₁, . . . , c_(l) y₁′, . . . , y_(k)′ is the codeword ofan error-correcting code C when no error occurred. As stated, the pairsof auxiliary read values [y₁′, y₂′], [y₃′, y₄′], . . . each only take onthree different values of four basically possible binary values each, sothat each of these pairs may be assigned to a memory state of a ternarymemory cell.

In contrast to that, depending on the value of the data bits, the pairsof check bits, for example [c₁, c₂], [c₃, c₄], . . . take on any of thepossible four different value combinations, as can be seen whenconsidering concrete codes, like linear codes, and as will be explainedlater for an embodiment. The check bits are here determined so that theyare an XOR combination of corresponding bits of the auxiliary readvalues according to the used code C.

According to an embodiment, as indicated above, the check bits of theauxiliary read values generated by the encoder are each stored in aseparate memory cell, while, for example, triples of data bits may bestored in two ternary memory cells, so that an error in a memory cell,that stores a check bit, may only affect one single check bit. As thenumber of the check bits is often low compared to the data bits or thenumber of the auxiliary read values, the required effort for storing theeach of the check bits in a separate memory cell is also low.

5. A corrector Cor 17 with l first binary inputs and k second binaryinputs and k binary outputs may exist, which is configured so thatdepending on the binary, possibly erroneous check bits c′=c₁′, . . . ,c_(l)′ applied at its first inputs and that depending on its binarypossibly erroneous auxiliary read values y′=y₁′, . . . , y_(k)′ appliedto its k binary inputs, the corrector Cor 17 outputs at its k binaryoutputs a k-component correction vector e=e₁, . . . e_(k) for correctingthe bits y₁′, . . . , y_(k)′ of the auxiliary read values. Then, thecorrection bits e₁, . . . , e_(k) are here described as a correctionerror e=e₁, . . . , e_(k).

For j=1, . . . , l when reading from the memory Sp 13, the data outputof the memory cell Spc_(j) is connected to the input of a subcircuittb_(j) 15 _(j), whose output is connected to the j-th input of the lfirst inputs of the corrector Cor 17. The subcircuit tb_(j) 15 _(j)transforms the ternary, possibly erroneous value c_(j) ^(t′) output bythe memory cell Spc_(j) into the binary value c_(j)′=tb_(j)(c_(j)^(t′)).

6. A combinational circuit Vkn 18 with 2·k binary inputs and k binaryoutputs may exist, which outputs, when inputting y₁′, . . . , y_(k)′ atits first k inputs and e₁, . . . , e_(k) at its second k inputs at its kbit output the corrected auxiliary read valuesy ^(cor) =y ₁ ^(cor) , . . . ,y _(k) ^(cor) =[y ₁ ′op ₁ e ₁ ], . . . ,[y_(k) ′op _(k) e _(k) ]=y′opewherein op₁, . . . , op_(k) are each uniquely invertible binaryoperations.

Here, the corrector Cor 17 and the combinational circuit Vkn 18 areimplemented so thaty=y ₁ , . . . ,y _(k) =[y ₁ ′op ₁ e ₁ ], . . . ,[y _(k) ′op _(k) e _(k)]=y′opeapplies, when an error, which may be corrected by the code C, exists.The bits y₁, . . . , y_(k) are here determined by the subsequenttransformations of the data bits x₁, . . . , x_(n) by the subcircuits BT11 and LH 16 asy ₁ , . . . ,y _(k) =LH[BT(x ₁ , . . . ,x _(n))].7. A subcircuit BB 19 may exist for the transformation of the k bitcorrected binary auxiliary read values y₁ ^(cor), . . . , y_(k) ^(cor)into the corrected binary output valuesx ₁ ^(cor) , . . . ,x _(n) ^(cor) =BB(y ₁ ^(cor) , . . . ,y _(k)^(cor)),wherein x₁ ^(cor), . . . , x_(n) ^(cor)=x₁, . . . , x_(n) applies whenan error exists which may be corrected by the code C.

The subcircuits BT 11, LH 16 and BB 19 are configured so thatBB{LH[BT(x ₁ , . . . ,x _(n))]}=x ₁ , . . . ,x _(n)applies, so that subsequent transformations of the data bits x₁, . . . ,x_(n) by the subcircuits BT 11, LH 16 and BB 19 reproduces the databits.

If no error occurred, a zero-correction vector e⁰=e₁ ⁰, . . . , e_(k) ⁰with y_(i)op_(i)e_(i) ⁰=y_(i) is output at the k outputs of thecorrector Cor 17.

The following examples provide embodiments with slight modifications:

The encoder Cod 12 may be modified so that it determines the check bitsc₁, . . . , c_(l) so that c^(i1), . . . , c_(l) ^(il) and y₁ ^(j1), . .. , y_(k) ^(jk) with y₁, . . . , y_(k)=LH[Tr1(x₁, . . . , x_(n))] form acodeword of an error-correcting code C with k data bits and l checkbits. Here, y_(j) ⁰= y _(j) and y_(j) ¹=y_(j) and accordingly c_(j) ⁰= c_(j) and c_(j) ¹=c_(j) so that the components of the auxiliary readvalues and the check bits may either be provided inverted ornon-inverted.

The corrector Cor 17 may be modified so that it provides the correctionvector in the form of e₁ ^(i1), . . . , e_(k) ^(ik), for example byinverters being connected to individual outputs of the same.

If all bits of the correction vector are provided non-inverted and ifall auxiliary read values are also provided non-inverted, then theoperations op_(i) may be chosen to be an XOR operation ⊕. If all bits ofthe correction vector are provided inverted and if all auxiliary readvalues are provided non-inverted, then the operations op_(i) may bechosen to be an XNOR operation.

In an embodiment, it may be further possible to exchange the order ofdifferent bits.

In order to make the description as easily understandable as possible,in the following the check bits, the bits of the correction vector andthe bits of the auxiliary read values are regarded to be non-inverted.In other embodiments, bits of the correction vector and/or bits of theauxiliary read values may be inverted.

If the error-correcting code C is a linear code which may becharacterized by a (k, k+l)-generator matrix or a G-matrix G=(l_(k),P_(k,l)), the following appliesc=c ₁ , . . . ,c _(l)=Cod(x ₁ , . . . ,x _(n))=(y ₁ , . . . ,y_(k))·P=LH[BT(x ₁ , . . . ,x _(n))]·P,wherein l_(k) is the k-dimensional binary identity matrix and P_(k,l) isa binary (k, l) matrix which is called the parity matrix of the code C.In this case, the check bits c₁, . . . , c_(l) also result bymultiplication of the error-free auxiliary read values y₁, . . . ,y_(k), which have been determined from the data values x₁, . . . ,x_(n), with the parity matrix P. As illustrated in FIG. 2, the encoderCod 12 then comprises a linear circuit Lin 21, downstream from thesubcircuit LH 22 and the subcircuit BT 23. The subcircuit LH 22 is equalto the subcircuit LH 16 of FIG. 1 d and the subcircuit BT 23 is equal tothe subcircuit BB 11 of FIG. 1 d. The subcircuit Lin 21 realizes themultiplication of the error-free auxiliary read values y₁, . . . ,y_(k)=LH[BT(x₁, . . . , x_(n))] with the parity matrix P.

A person skilled in the art may optimize the series connection of thecircuits of LH and BT together.

The corrector Cor 17 is configured so that in case of an error, whichmay be corrected by the code C in the auxiliary read values y₁′, . . . ,y_(k)′ and the check bits c₁′, . . . , c_(l)′ is determined by thecorrection bits e₁, . . . , e_(k) of the auxiliary read values y₁′, . .. , y_(k)′ for the considered error-correcting code C, wherein y₁′, . .. , y_(k)′ are possibly erroneous auxiliary read values determined bythe circuit LH 16 of the reading out possibly erroneous state values z₁′. . . , z_(m)′, z_(m+1)′, . . . , z_(M)′ from the memory 13. The bitsc₁′, . . . , c_(l)′ are the check bits which are possibly erroneousafter reading out of the memory 13.

Now, the functioning of the circuitry of FIG. 1 d is to be described.The sequence x₁, . . . , x_(n) of binary data to be stored is appliedboth to the n bit input of the subcircuit BT 11 and also to the n bitinput of the encoder Cod 12. At its M outputs the subcircuit BT 11outputs the values z₁, . . . , z_(m) to be stored in the memory Sp 13.Here, the values z₁, . . . , z_(m) are each analog values, which areinterpreted as three different values, e.g. as ternary values, dependingon their assignment to one of three different non-overlapping intervals.

In order to emphasize that these are ternary or binary values, ternaryvalues are designated as ter₁, ter₂, ter₃ or as 0_(ter), 1_(ter),2_(ter) while binary values are designated as 0_(bin) and 1_(bin). Ifternary values or states are written into different memory cells A and Bor read from the same, they are also designated as A₀, A₁, A₂ or B₀, B₁,B₂ to be able to differentiate the same better.

Here, the ternary values 0_(ter), 1_(ter), 2_(ter) are designated sothat the analog values corresponding to 0_(ter), and 1_(ter) belong tointervals which are adjacent just like the analog values whichcorrespond to 1_(ter), and 2_(ter) also belong to adjacent orneighboring intervals. In this respect, the ternary values 0_(ter), and1_(ter) just like the ternary values 1_(ter), and 2_(ter) areneighboring values. The ternary values 0_(ter), and 2_(ter) are notneighboring.

The ternary values z₁, . . . z_(m) are stored into memory cells of thememory Sp 13 with ternary states.

The output values z₁₊₁, . . . , z_(M) of the subcircuit BT 11 are suchoutput values which only each take on at most two different values. Itis here possible that z_(j) for jε{m+1, . . . , M} takes on two of thethree basically possible three ternary values, for example, the ternaryvalues 0_(ter) and 2_(ter) or also two binary values 0 and 1.

If z_(j) takes on binary values 0, 1, then z_(j) may be stored in abinary memory cell of the memory Sp 13. z_(j) may also be stored in aternary memory cell of the memory Sp 13. Then, only two differentternary values are written into the corresponding ternary memory cell.Based on a possible error, in principle also the third memory state maybe taken on by the considered memory cell.

The memory cells for storing the values z₁, . . . , z_(m) are thusmemory cells whose states may take on ternary values, and the memorycells for storing the values z_(m+1), . . . , z_(M) are memory cellswhose states may take on at least two different values.

At its l bit wide output, the encoder Cod 12 outputs l binary check bitsc₁, . . . , c_(l), which are also stored in the memory Sp 13 in memorycells, which may take on at least two different states.

Depending on the implementation, binary memory cells or ternary memorycells may be used, whose state when writing each only takes on twodifferent values.

In FIG. 1 d, the case is illustrated that the check bits c₁, . . . ,c_(l) output by the encoder 12 are stored in ternary memory cells.

For j=1, . . . , l, the j-th output of the encoder Cod 12, which carriesthe binary value c_(j), is fed into the input of a subcircuit bt_(j) 14j which outputs a corresponding ternary value c_(j) ^(t)=bt_(j)(c_(j))at its outputs, which is stored in the ternary memory cell Spc_(j) whenwriting. If no error is present, then only two of the possible threeternary values may occur as states of the memory cell Spc_(j). Due to anerror also the third possible third ternary value may be stored as astate.

When reading, from the memory Sp 13 the possibly erroneous values z₁′, .. . , z_(m)′, z_(m+1)′, . . . , z_(M)′ and the possibly erroneous checkbits c₁ ^(t′), . . . , c_(l) ^(t′) are read out which may differ fromthe corresponding correct values due to errors which may, for examplehave occurred during storing.

For j=1, . . . , l, the output of the memory cell Spc_(j) which carriesthe signal c_(j) ^(t′) when reading, is connected to the input of thesubcircuit tb_(j) 15 j, which transforms the ternary signal c_(j) ^(t′)into the binary signal c_(j)′=tb_(j)(c_(j) ^(t′)).

If no error occurred, then the check bit c_(j) is provided by theencoder at the output of the subcircuit tb_(j) 15 j, which is connectedto the j-th input of the first l inputs of the corrector Cor 17.

The values z₁′, . . . , z_(m)′, z_(m+1)′, . . . , z_(M)′ read out of thememory Sp 13 are transformed by the subcircuit LH 16 into k binaryauxiliary read values y′=y₁′, . . . y_(k)′.

The binary auxiliary read values y′=y₁′, . . . y_(k)′ are fed into thesecond k binary inputs of the corrector Cor 17.

The corrector Cor 17 outputs at its k binary outputs the correctionvalues e=e₁, . . . , e_(k) for the auxiliary read values y′=y₁′, . . .y_(k)′, which are corrected in the combinational circuit Vkn 18 into thecorrected auxiliary read valuesy ^(cor) =y ₁ ^(cor) , . . . ,y _(k) ^(cor) =[y ₁ ′op ₁ e ₁ ], . . . ,[y_(k) ′op _(k) e _(k)]and which are input into the subcircuit BB 19.

The subcircuit BB 19 transforms the corrected auxiliary read valuesy^(cor)=y₁ ^(cor), . . . , y_(k) ^(cor) into the corrected output valuesx ^(cor) =x ₁ ^(cor) , . . . ,x _(n) ^(cor) =BB(y ₁ ^(cor) , . . . ,y_(k) ^(cor)).

If no error is present, the following applies

$\mspace{20mu}{z_{1}^{\prime},\ldots\mspace{14mu},{z_{M}^{\prime} = z_{1}},\ldots\mspace{14mu},z_{M},\mspace{20mu} c_{1}^{\prime},\ldots\mspace{14mu},{c_{l}^{\prime} = c_{1}},\ldots\mspace{14mu},c_{l},y_{1}^{\prime},\ldots\mspace{14mu},{y_{k}^{\prime} = y_{1}},\ldots\mspace{14mu},{y_{k} = {{{LH}\left( {z_{1},\ldots\mspace{14mu},z_{M}} \right)} = {{LH}\left\lbrack {{BT}\left( {x_{1},\ldots\mspace{14mu},x_{n}} \right)} \right\rbrack}}},\mspace{20mu}{e = e_{1}},\ldots\mspace{14mu},{e_{k} = \underset{\underset{k}{︸}}{0,\ldots\mspace{14mu},0}},\mspace{20mu} y_{1}^{cor},\ldots\mspace{14mu},{y_{k}^{cor} = y_{1}},\ldots\mspace{14mu},{y_{k}\mspace{14mu}{and}}}$  x^(cor) = x₁^(cor), …  , x_(n)^(cor) = x₁, …  , x_(n) = x,and the output of the stored sequence x is error-free.

If errors occur in the data, read out of the memory Sp 13, then theoutput of the stored sequence x^(cor) is error-free, if the errors inthe check bits c₁′, . . . c_(l)′ and the errors caused by the errors inthe output values z₁′, . . . , z_(M)′ in the binary auxiliary readvalues y₁′, . . . , y_(k)′ are correctable by the code C, and if theerrors are corrected.

The correction is done by the corrector Cor 17 which forms a k-digitcorrection value e=e₁, . . . , e_(k), which depends on the check bitsc₁′ . . . c_(l)′ read out of the memory Sp 13 and the auxiliary readvalues y₁′, . . . , y_(k)′, wherein the corrector Cor 17 forms thecorrection values e₁, . . . , e_(k) which are component-wise combinedwith y₁′, . . . , y_(k)′ in the combinational circuit Vkn 18, whereinthe auxiliary read values y^(cor)=y₁ ^(cor), . . . , y_(k) ^(cor) aretransformed by the subcircuit BB 19 into the n-digit binary outputsequence x₁ ^(cor), . . . , x_(n) ^(cor).

When memory errors occur, ternary states of the memory cells may change.The correction of possible memory errors of the ternary memory Sp 13 isexecuted, as described above, by the correction of the binary auxiliaryread values y′=y₁′, . . . , y_(k)′ using binary check bits c₁′, . . . ,c_(l)′. The binary auxiliary read values are read out of the ternarymemory with possibly erroneous ternary state values z₁′, . . . , z_(M)′.According to embodiments, the associated binary check bits for theauxiliary read values are formed by the encoder Cod 12 directly asbinary check bits c₁, . . . , c_(l) from the binary input sequence x₁, .. . , x_(n).

According to embodiments, they are each stored in a separate memory cellas ternary values c₁ ^(t), . . . , c_(l) ^(t) and read out of the memorycells Spc₁, . . . , Spc_(l) as possibly erroneous ternary values c₁^(t′), . . . , c_(l) ^(t′) and transformed by the subcircuits tb₁, . . ., tb_(l) into possibly erroneous checkbits c₁′, . . . , c_(l)′.

Again, it should be noted here, that a pair of binary auxiliary readvalues assigned to a ternary memory state only takes on three differentbinary values and may thus be read out as information from one singleternary memory cell. A pair of binary check bits, however, generallytakes on four different values so that the binary check bits accordingto embodiments are each stored in a separate memory cell (ternary orbinary).

Thus, it is possible for correcting errors in a three-value memory tosensibly use binary error-correcting codes, like e.g. binary Hammingcodes, binary Hsiao codes, binary BCH codes for error-correcting errorsin ternary memories.

A person skilled in the art understands that equivalent transformations,like, for example, inverting bits in the circuitry Cir₁ do not changethe nature of the embodiments. For example, it is thus possible that thecorrector Corr 17 outputs partially inverted components, instead ofoutputting the components e₁, . . . , e_(k) of the correction vector efor the possibly erroneous auxiliary read values y₁′ . . . y_(k)′, e.g.instead of component e₁, component ē₁, which is then combined with y₁′to y₁ ^(c)= y₁′⊕{overscore (e)}₁ . If for example the combination op₁ isoriginally realized as an XOR operation or combination, then it is to bereplaced by an XNOR operation when the component e₁ is replaced by thecomponent ē₁.

Likewise, it is, for example, possible that the encoder Cod 12 outputspartially inverted check bits, whose inversion is balanced by theimplementation of the corrector Corr 17.

Apart from that, it is, for example, possible jointly to optimizedifferent circuit parts together like using a hardware descriptionlanguage as is conventional in circuits design.

FIG. 1 e depicts circuitry according to an embodiment comprising acircuitry according to FIG. 1 d which is supplemented by an errordetection circuit Det 120. In the embodiment of FIG. 1 e, thecombinational circuit Vkn 18 of FIG. 1 d is realized as an XOR circuit18 a.

The subcircuits of FIG. 1 e which correspond to the subcircuits in FIG.1 d are marked with the same reference numerals and have already beendescribed above. The error detection circuit Det 120 comprises k+lbinary inputs and an r bit wide binary output carrying the error signalE, wherein r≧1. k first inputs of the error detection circuit areconnected to the k outputs of the subcircuit LH 16, which carry theauxiliary read values y′=y₁′, . . . , y_(k)′. The further l binaryinputs are connected to the outputs of the subcircuits tb₁, 151 . . . ,tb_(l), 15 l, which carry the read out check bits c₁′, . . . , c_(l)′when reading.

The r bit wide output of the error detection circuit Det 120 carries anerror signal E, wherein the value of the error signal E indicateswhether y₁′, . . . , y_(k)′, c₁′, . . . , c_(l)′ is a code word of thecode C (no detectable error) or whether y₁′, . . . , y_(k)′, c₁′, . . ., c_(l)′ is no codeword of the code C (detectable error).

If for example r=1, the error detection circuit, Det may be configuredso that E=0 indicates that no detectable error is present in theauxiliary read values y₁′, . . . , y_(k)′ and the check bits c₁′, . . ., c_(l)′ and that E=1 indicates that a detectable error exists in thesebits.

If, for example, r=2, the value E=(1,0) or E=(0,1) may indicate that nodetectable error occurred, and the value E=(0,0) or E=(1,1) may indicatethat a detectable error occurred.

It is further possible to design the error detection circuit Det so thatthe output error signal E is different for different types of errors,like 1 bit errors, 2 bit errors, . . . , as it is obvious to a personskilled in the art for different codes and as it will be described laterfor a concrete code.

The error detection circuit Det 120 and the corrector Korr 16 comprisethe same input values and they may also be jointly optimized, as it isconventional in circuit design and may automatically be executed by adesign compiler when the design is for example executed using a hardwaredescription language.

Now, the formation of the auxiliary read valuesy′=y ₁ ′, . . . ,y _(k) ′=LH(z ₁ ′, . . . ,z _(m) ′,z _(m+1) ′, . . . ,z_(m)′)by a subcircuit LH 16 is described.

For example, by the subcircuit LH 16, to each ternary component z_(i)′with iε{1, . . . , M} a t_(i)-tuple L(z_(i)′) binary values may beassigned, forming the auxiliary read valuesy′=y ₁ ′, . . . ,y _(k) ′=L ¹(z ₁′), . . . ,L ^(M)(z _(M)′)

Here, 2≦t_(i) for 1≦i≦m and 1≦t_(i) for m+1≦i≦M. If, for example,t_(i)=2, then such an assignment of z_(i)′ to a tuple L^(i)(z_(i)′)=L₁^(i)(z_(i)′), L₂ ^(i)(z_(i)′) of binary values may easily be realized bya component-wise analog-to-digital conversion. Thus, for example, aternary value of a component z_(i)′ representing an analog physicalvalue and belonging to a certain non-overlapping interval may simply bedigitized into two binary values.

For q=3 possible values this may, for example, simply be executed usingq−1=2 comparator with reference values R₁, R₂ with R₂<R₁. If z_(i)′>R₁then L₁ ^(i)(z_(i)′)=1. If z_(i)′≦R₁ then L₁ ^(i)(z_(i)′)=0, ifz_(i)′>R₂ then L₂ ^(i)(z_(i)′)=1, if z_(i)′≦R₂ then L₁ ^(i)(z_(i)′)=0.In this simple way to a value z_(i)′ a tuple of binary values may beassigned designated as auxiliary read values, so that the followingappliesL ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=0,0 for z _(i) ′≦R ₂L ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=0,1 for R ₂ <z _(i)′≦R ₁L ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=1,1 for z _(i) ′≧R₁.

In this case, a binary coding of the analog values result with thecharacteristic that two analog values which only slightly differregarding the analog value and which belong to the neighboringintervals, digital tuples are assigned which only differ in one bit.Such an assignment of analog values to digital values is conventionallyused by a person skilled in the art of digitizing analog values so thatwith a small change of the analog values the associated digital valueonly changes by one bit which was, for example, proposed in Steinbuch,K., Rupprecht, W. Nachrichtentechnik, Springer Verlag,Berlin/Heidelberg/New York 1967, page 339.

A further assignment possibility may, for example, be that to a ternaryvalue said z_(i)′ a triple of binary auxiliary read valuesL^(i)(z_(i)′)=L₁ ^(i)(z_(i)′), L₂ ^(i)(z_(i)′), L^(i)(z_(i)′) is alsoassigned by an analog-to-digital conversion, wherein the differenttriples form a 1 of 3 code.

This may, for example, also be done using two comparisons with tworeference values R₁, R₂ with R₂<R₁.

If z_(i)′>R₁, then L(z_(i)′) may be determined to be 1,0,0. IfR₂<z_(i)′≦R₁, L(z_(i)′) may be determined to be 0,1,0, and if z_(i)′≦R₂,L(z_(i)′) may be determined to be 0,0,1. In this simple way then to aternary value z_(i)′, a triple of binary values is assigned so that eachof the triples of binary values comprises exactly one 1 and thefollowing appliesL(z _(i)′)=1,0,0 für z _(i) ′>R ₁L(z _(i)′)=0,1,0 für R ₂ <z _(i) ′≦R ₁L(z _(i)′)=0,0,1 für z _(i) ′≦R ₂.

It is illustrated in FIG. 1 f that the memory Sp 13 comprises a ternarymemory Sp_(ter) 131 of memory cells which may take on three differentvalues and a binary memory Sp_(bin) 132 of memory cells which may takeon two different values. The outputs of the encoder Cod 12 which carrythe binary check bits c=c₁, . . . , c_(i) are, when writing, directlyconnected to the data inputs of the corresponding memory cells of thebinary memory Sp_(bin), while when reading, the data outputs of thememory cells which carry the possibly erroneous check bits c₁′, . . . ,c_(l)′ are directly connected to the corresponding inputs of thecorrector Corr 17.

FIG. 1 f illustrates that the output values z₁, . . . , z_(m), z_(m+1),. . . , z_(M) of the subcircuit BT 11 are stored in memory cells of theternary memory Spei_(tern) 131, while the binary output values c₁, . . ., c_(l) of the encoder Cod 12 are stored in cells of the binary memorySpei_(bin) 132. Storing should be realized in one embodiment so that theoutput values z₁, . . . , z_(m), z_(m.+1 . . . ,) z_(M) of thesubcircuit BT 11 and the associated binary output values c₁, . . . ,c_(l) of the encoder Cod 12 are stored in the memory Sp_(ter) 131 andthe memory Sp_(bin) 132 at the same address.

As the values z_(m+1), . . . , z_(M) only take on two different valueseach, in another embodiment, these values may also be stored in a binarymemory Sp_(bin).

Possible implementations of the subcircuit BT 11 of FIG. 1 a are now tobe explained in more detail.

FIG. 3 a shows, for n=9 and M=6, one possible realization of thesubcircuit BT 11. At its nine binary inputs, the binary values x₁, x₂, .. . , x₉ are applied, and at its six ternary outputs, six ternary valuesz₁, . . . , z₆ are output. The realization is set up from threesubcircuits BT₁ 31, BT₂ 32 and BT₃ 33 for realizing three functions f₁,f₂ and f₃, wherein these subcircuits each comprise three binary inputsand two ternary outputs.

The subcircuit 31 realizes the function f₁ with f₁(x₁, x₂, x₃)=z₁, z₂.

The subcircuit 32 realizes the function f₂ with f₂(x₄, x₅, x₆)=z₃, z₄.

The subcircuit 33 realizes the function f₃ with f₃(x₇, x₈, x₉)=z₅, z₆.

As there are eight different binary triples of values of three variablesand nine tupels of values of two ternary variables, the eight possiblebinary input values are each mapped by the functions f₁, f₂ and f₃ toeight different pairs of ternary output values each. Mapping is executedso that different triples of binary input values correspond to differenttupels of ternary output values. Concrete implementations are explainedlater.

FIG. 3 b shows for n=11 and M=8, a further possible realization of thesubcircuit BT 11. At its eleven binary inputs, the binary values x₁, x₂,. . . , x₁₁ are applied and at its eight ternary outputs the eightternary values z₁, . . . , z₈ are output. The realization is set up fromfour subcircuits BT₁ 34, BT₂ 35, BT₃ 36 and BT₄ 37 for realizing fourfunctions f₁, f₂, f₃ and f₄, wherein these subcircuits each comprisethree binary inputs and two ternary outputs.

The subcircuit 34 realizes the function f₁ with f₁(x₁, x₂, x₃)=z₁, z₂.

The subcircuit 35 realizes the function f₂ with f₂(x₄, x₅, x₆)=z₃, z₄.

The subcircuit 36 realizes the function f₃ with f₃(x₇, x₈, x₉)=z₅, z₆.

The subcircuit 37 realizes the function f₄ with f₄(x₁₀, x₁₁, 0)=z₇, z₈.

In FIG. 3 b for the subcircuit BT₄ 37 which realizes the functionf₄(x₁₀, x₁₁)=z₇, z₈ and which depends on the two binary variables x₁₀,x₁₁, a further input is plotted which carries the constant value 0. Bythis, it is to be illustrated that the subcircuit 37 may for example bederived from subcircuit 36 for realizing the function f₃, by, forexample, constantly setting the value, for example, of the third inputvariable to 0, so that the following formula applies:f ₄(x ₁₀ ,x ₁₁)=f ₃(x ₁₀ ,x ₁₁,0).

FIG. 3 c shows, for n=8 and M=6, a further possible realization of thesubcircuit BT 11. At its eight binary inputs the binary values x₁, x₂, .. . , x₈ are applied and at its six ternary outputs the six ternaryvalues z₁, . . . , z₆ are output. The realization is set up from foursubcircuits BT₁ 38, BT₂ 39, BT₃ 310 and BT₄ 311 for realizing twofunctions f and φ, wherein the function ƒ is realized by subcircuits 38and 39 and the function φ is realized by subcircuits 310 and 311. Thesubcircuits 38 and 39 for realizing the function f comprise three binaryinputs and two ternary outputs. The subcircuits 310 and 311 forrealizing the function φ comprise each one binary input and an outputwhich may take on two different values.

The subcircuits 38 and 39 realize the same function f with f (x₁, x₂,x₃)=z₁, z₂ and f (x₄, x₅, x₅)=z₃, z₃ and the subcircuits 310 and 311each realize the function φ with φ(x₇)=z₅ and φ(x₈)=z₆. The followingapplies herez _(m+1) =z ₅ and Z _(M) =z ₆.

Accordingly, the circuits 310 and 311 may be implemented for realizingthe function φ so that, for example, φ(0_(bin))=0_(ter) andφ(1_(bin))=2_(ter) or φ(0_(bin))=0_(ter) andφ(1_(bin))=1_(tern)=1_(bin). If φ(1_(bin))=2_(tern), then the binaryvalue 1_(bin) is transformed by the subcircuits 310 and 311 forrealizing the function φ into the ternary value 2_(ter), so that thevalues z₅ and z₆ output at the respective output of the subcircuit 210and 211 are stored into memory cells of the memory Sp 13 whose statestake on ternary values.

If φ(1_(bin))=1_(ter)=1_(bin), then the values z₅ and z₆ output at theoutput of the subcircuits may be stored both in memory cells of thememory Sp 13 which take on ternary values as well as in memory cellswhich take on binary values.

The auxiliary read values y′=y₁′, . . . , y_(k)′:y′=y ₁ ′, . . . y _(k) ′=LH(z ₁ ′ . . . ,z _(m) ′,z _(m+1) ′, . . . ,z_(M)′)are formed by the subcircuit LH 16 from the state values z₁′ . . . ,z_(m)′, z_(m+1)′, . . . , z_(M)′output from the memory Sp 13.

It is illustrated in FIG. 4, how in one embodiment the subcircuit LH 16for forming the auxiliary read values may be set up from M subcircuitsLH¹ 161, . . . , LH^(m) 16 m, LH^(m+1), 16(m+1), . . . , LH^(M) 16M.

In the embodiment illustrated by FIG. 4, for i=1, . . . , M, a t_(i)tuple L^(i)(z_(i)′) of binary values is associated with the componentz_(i)′ by the subcircuit LH^(i) 16 i, wherein the binary values form theauxiliary read values arey′=y ₁ ′, . . . y _(k) ′=L ¹(z ₁′), . . . ,L ^(M)(z _(M)′).

Here, 2≦t_(i) for 1≦i≦m and 1≦t_(i) for m+1≦i≦M.

First of all the case is considered that 1≦i≦m.

If for example t_(i)=2 or i=1, . . . , m, then such an assignment ofz_(i)′ to a tuple L^(i)(z_(i)′)=L₁ ^(i)(z_(i)′), L₂ ^(i)(z_(i)) ofbinary auxiliary read values may simply be realized by ananalog-to-digital conversion of z_(i) by a subcircuit LH^(i) 16 i. Thus,for example, a ternary value of a component z_(i)′ which represents ananalog physical value and which belongs to a certain non-overlappinginterval may simply be digitized into two binary values.

This may, for example, simply be done using two comparators havingreference values R₁, R₂ with R₂<R₁. If z_(i)′>R₁ then L₁ ^(i)(z_(i)′)=1.If z_(i)′≦R₁ then L₁ ^(i)(z_(i)′)=0. If z_(i)′>R₂ then L₂^(i)(z_(i)′)=1. If z_(i)′≦R₂ then L₁ ^(i)(z_(i)′)=0. By this, a tuple ofbinary values may be associated to a value z_(i)′, wherein the binaryvalues are designated as auxiliary read values, so that the followingappliesL ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=0,0 for z _(i) ′≦R₂.L ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=0,1 for R ₂ <z _(i)′≦R ₁.L ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=1,1 for z _(i) ′≧R₁.

It is also possible to do the assignment, so that the following appliesL ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=0,0 for z _(i) ′≦R₂.L ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=1,0 for R ₂ <z _(i)′≦R ₁.L ^(i)(z _(i)′)=L ₁ ^(i)(z _(i)′),L ₂ ^(i)(z _(i)′)=1,1 for z _(i) ′≧R₁.

A further assignment possibility may for example be that to a ternaryvalue z_(i)′ by a subcircuit LH^(i) 16 i a triple or binary valueL^(i)(z_(i)′)=L₁ ^(i)(z_(i)′), L₂ ^(i)(z_(i)′), L₃ ^(i)(z_(i)′) is alsoassigned by analog-to-digital conversion, wherein the different triples,for example, form a 1 of 3 code.

For example, this may also be done using two comparators with tworeference values R₁, R₂ with R₂<R₁ as it was already described, so thatthe following appliesL ^(i)(z _(i)′)=1,0,0 for z _(i) ′>R ₁L ^(i)(z _(i)′)=0,1,0 for R ₂ <z _(i) ′≦R ₁L ^(i)(z _(i)′)=0,0,1 for z _(i) ′≦R ₂

It is also possible to assign a triple of binary values to a ternaryvalue z_(i) so that each triple of binary values contains exactly one 0and for example the following appliesL ^(i)(z _(i)′)=1,1,0 for z _(i) ′>R ₁L ^(i)(z _(i)′)=0,1,1 for R ₂ <z _(i) ′≦R ₁L ^(i)(z _(i)′)=1,0,1 for z _(i) ′≦R ₂

It is also possible that for 1≦i≦m, all subcircuits LH¹ 161, . . . ,LH^(m) 16 m are equal.

Now the case is considered that m+1≦j≦M. z_(j)′ is input into thesubcircuit LH^(j), wherein z_(j)′ only takes on two different valueswhen writing in, and thus z_(j)′=z_(j) in the error-free case whenreading out.

Differences result depending on whether z_(j) is stored in a ternarymemory cell or in a binary memory cell.

First of all, the case is considered that z_(j)′ is stored in a ternarymemory cell with three possible state values. Although the value z_(j)which was written in may only take on two different values, in this casethe read out value z_(j)′, due to a memory error, may take on threedifferent values.

If the binary values 0_(bin) and 1_(bin) were encoded by the subcircuitBT₃ 310 or BT₄ 311 in FIG. 3 c as 0_(ter) and 2_(ter), respectively, thecorresponding subcircuit LH^(j) may for example realize the mappingL^(j)(0_(ter))=0_(bin), LH^(j)(1_(ter))=1_(bin) andLH^(j)(2_(ter))=1_(bin). Such a realization has the advantage that amemory error which corrupts the ternary value 2_(ter) into 1_(ter) istolerated as it has no effect at the output of the circuit L^(j).

The subcircuit L^(j) may, for example, be realized using a comparatorwhich compares the value z_(j) to a reference value R₁, so that thefollowing appliesLH ^(j)(z _(j))=0_(bin) for z _(j) ′≦R ₁.LH ^(j)(z _(j))=1_(bin) for z _(j) ′>R ₁.

If, on the other hand, z_(j) is stored in a binary memory, the state ofthe memory cell may only take on two different values. In this case,both the value z_(j) written into the binary memory cell and also thevalue z_(j)′ read out of this memory cell are binary, so that this readout value z_(j)′ may directly serve as an auxiliary read value and thecorresponding subcircuit LH^(j) may consist of a line which directlyconnects its input to its output.

FIG. 5 a illustrates how the encoder Cod 12 is functionally realized.Functionally, the encoder 12 includes a series connection of thesubcircuit BB 11, LH 16 and a subcircuit BinCod 51 having k binaryinputs and l binary outputs. As the subcircuit BB 11 and LH have alreadybeen described, here only the subcircuit BinCod 51 is to be described.

The subcircuit BinCod 51 is implemented so that it forms the l binarycheck bits c₁, . . . , c_(l) from the binary values y₁, . . . , y_(k)applied at its input. Here, the values y₁, . . . , y_(k) are the kinformation bits of a binary code BinC and c₁, . . . , c_(l) are theassociated check bits, so that the subcircuit BinCod 51 simply forms thecorresponding binary check bits c₁, . . . , c_(l) of the informationbits y₁, . . . , y_(k) of the code C. The code C may here be a linear ora non-linear code.

A person skilled in the art may optimize the circuit functionalitydescribed by FIG. 5 a using a synthesis tool as it is conventional incircuit design.

It is illustrated in FIG. 5 b how the encoder Cod 12 may functionally berealized when the error-correcting code C is a linear code which may bedescribed by a (k, k+l)-G-matrix G=(l_(k), P_(k,l)). Here, l_(k) is a(k)-dimensional identity matrix and P_(k,l) is a (k, l) matrix which isto be referred to as a parity matrix.

In contrast to FIG. 5 a, the subcircuit BinCode 51 is replaced by thesubcircuit LinCode 52. The subcircuit LinCode 52 is implemented so thatit forms the binary check bits c₁, . . . , c_(l) output at its l binaryoutputs according to the relationc ₁ , . . . ,c _(l)=(y ₁ , . . . ,y _(k))·P,from the values y₁, . . . , y_(k) applied to its inputs. It may begathered that the subcircuit LinCode is a conventional circuit fordetermining the check bits c₁, . . . , c_(l) of the linearerror-correcting code C from the bits y₁, . . . , y_(k) with thegenerator matrix G=(l_(k), P_(k,l)). In this sense, the bits y₁, . . . ,y_(k) are the information bits of the code C. The code C may for examplebe a Hamming code, a Hsiao code, a BCH code or another linearerror-correcting code.

A person skilled in the art will optimize the circuit functionallydescribed by FIG. 5 b for example using a synthesis tool as it isconventional in circuit design.

It is illustrated in FIG. 5 c how the encoder Cod 12 may be functionallyrealized when the check bits c₁, . . . , c_(l) also depend on theaddress bits of the write address a=a₁, . . . , a_(Q). Theerror-correcting code C was assumed to be a linear code which may bedescribed by a (k+q, k+q+l)-G matrix G=(l_(k+q), P_(k+q,l)). Here,l_(k+q) is a (k+q)-dimensional identity matrix and P_(k+q,l) a (k+q,l)-matrix which is to be referred to as a parity matrix. Apart from thedata bits x=x₁, . . . , x_(n), the check bits c₁, . . . , c_(l), alsodepend on q bits A₁, . . . , A_(q), which are determined from theaddress bits a₁, . . . , a_(Q) asA ₁ , . . . ,A _(q) =F(a ₁ , . . . ,a _(Q))

Here, a=a₁, . . . , a_(Q) is the address under which z₁, . . . , z_(m),z_(m+1), . . . , z_(M) and the check bits c=c₁, . . . , c_(l) arewritten into the memory Sp 13. Q is the word width of the write addressa and q≦Q applies. F describes a unique mapping of the Q bits of thewrite address to q bits A₁, . . . , A_(q).

The corresponding encoder is illustrated in FIG. 5 c. In FIG. 5 c, thesubcircuit Lincode 53 comprises k first inputs to which the auxiliaryread values y₁, . . . , y_(k) output by the subcircuit LH are applied,and q second inputs connected to the q outputs of the subcircuit F_(S).At its l outputs, the subcircuit F_(s) 55 outputs the bits A₁, . . . ,A_(q), determined by the function F from the address bits a=a₁, . . . ,a_(Q), wherein the subcircuit F_(S) 55 realizes the function F. At its lbinary outputs, the subcircuit Lincode 53 outputs the check bits c₁, . .. , c_(l).

In contrast to this, the subcircuit Lincode 52 of FIG. 5 b onlycomprises k inputs to which the auxiliary read values y₁, . . . , y_(k)are applied.

For a linear code which may be described by a (k+q, k+q+l)-G-matrixG=(l_(k+q), P_(k+q,l)), the l binary check bits c₁, . . . , c_(l) aredetermined according to the relationc ₁ , . . . ,c _(l)=(y ₁ , . . . ,y _(k) ,A ₁ , . . . ,A _(q))·P.

If, for example, q=1 and A₁=a₁⊕ . . . ⊕a_(Q), then A₁ is the parity ofthe write address and for the check bits c₁, . . . , c_(l) the followingappliesc ₁ , . . . ,c _(l)=(y ₁ , . . . ,y _(k) ,A ₁)·P,wherein the G matrix G is a (k+1, k+l+1) matrix and P is a (k+1, l)matrix.

In FIG. 5 d, the corresponding encoder 58 is illustrated. The subcircuit56 has k+1 inputs, wherein the k auxiliary read values y₁, . . . , y_(k)are applied to k first inputs. The (k+1)th input is connected to the1-bit wide output of an XOR circuit 57 which outputs at its output theparity A₁=a₁⊕ . . . ⊕a_(Q) of the address bits.

If q=Q and A₁, . . . , A_(Q)=a₁, . . . , a_(Q), then the check bits c₁,. . . , c_(l) depend on all bits of the write address a. For a linearcode which may be described by a (k+Q, k+Q+l)-G-matrix G=(l_(k)+Q,P_(k+Q,l)), the l binary check bits c₁, . . . , c_(l) are determinedaccording to the relationc ₁ , . . . ,c _(l)=(y ₁ , . . . ,y _(k) ,a ₁ , . . . ,a _(Q))·P.

In FIG. 5 e the corresponding encoder 510 is illustrated. The subcircuit59 Lincode comprises k+Q inputs, wherein to k first inputs k auxiliaryread values y₁, . . . , y_(k) are applied. At the Q second inputs theaddress bits a₁, . . . , a_(Q) of the write address are applied.

A person skilled in the art understands that when the check bits alsodepend on address bits of the write address, a non-linearerror-correcting code may be used instead of a linear code.

FIG. 6 a shows a conventional realization of a corrector for a linearerror-correcting code C. The code C of the length k+l with k informationbits, here the auxiliary read values y₁′, . . . , y_(k)′, and l checkbits, here the check bits c₁′, . . . , c_(l)′, may be described by acorresponding H matrix H, which may exist in a systematic form H=(P^(T),l_(l)) or in a non-systematic form.

The corrector Cor 17 a for the considered linear error-correcting code Cin FIG. 6 a comprises a syndrome generator 61 a conventional for linearcodes having l+k binary inputs and l binary outputs and a decoder 62 awith l binary inputs and k binary outputs. The l data outputs of thememory Sp 13 which carry the possibly erroneous values c₁′, . . . ,c_(l)′ of the check bits, when reading, are fed into l first inputs ofthe syndrome generator 61 a, while the k outputs of the subcircuits LH16 which carry the possibly erroneous auxiliary read values y′=y₁′, . .. , y_(k)′ are connected to the further k inputs of the syndromegenerator 61 a. The l outputs of the syndrome generator 61 a areconnected to the l inputs of the decoder 62 a which outputs the kcomponent correction vector e=e₁, . . . , e_(k) at its k outputs. Thesyndrome generator 61 a is implemented, so that at its l binary outputsit outputs the components s₁, . . . , s_(l) of the error syndrome s,which is determined bys ₁ , . . . ,s _(l) =H·[y ₁ ′, . . . ,y _(k) ′,c ₁ ′, . . . ,c_(l)′]^(T).

If the code C is a K bit error-correcting code, then to each M bit errorwith M≦K a separate error syndrome is associated and the error may becorrected on the basis of the syndrome.

The decoder 62 a may be implemented as a combinational circuit whichoutputs the k-digit correction vector e=e₁, . . . , e_(k) when inputtingthe syndrome. If M≦K, then exactly those components of the correctionvector e=e₁, . . . , e_(k) are equal to 1 at which an error occurred andwhich are corrected.

The correction takes place in the combinational circuit Vkn 18 which inthe embodiments of FIG. 1 e is implemented as an XOR circuit 18 a, sothat y₁′⊕e₁ . . . , y_(k)′⊕e_(k)=y₁ ^(c), . . . , y_(k) ^(c) is formed.

It is illustrated in FIG. 6 b how the corrector may be functionallyrealized as Cor 17 b, wherein the check bits c₁, . . . , c_(l) alsodepend on the address bits of the write address a=a₁, . . . , a_(Q).Apart from the auxiliary read values y₁′, . . . , y_(k)′ and the checkbits c₁′, . . . , c_(l)′, in FIG. 6 b, the error syndrome s=s₁, . . . ,s_(l) also depends on q bits A₁′, . . . , A_(q)′, which are determinedfrom the address bits a′=a₁′, . . . , a_(Q)′ of the read address a′ asA ₁ ′, . . . ,A _(q) ′=F(a ₁ ′, . . . ,a _(Q)′).

Here, a′=a₁′, . . . , a_(Q)′ the address under which the auxiliary readvalues y₁′, . . . , y_(k)′ and the check bits c′=c₁′, . . . , c_(l)′ areread from the memory Sp 13. Q is the word width of the read address a′,and the following applies q≦s Q. F describes the same unique mapping ofthe Q bits of the read address a′=a₁′, . . . , a_(Q)′ to q bits A₁′, . .. , A_(q)′, as it was used in mapping the write address a=a₁, . . . ,a_(Q) to the bits A₁, . . . , A_(q).

The syndrome generator 61 b is now implemented so that it outputs at itsl binary outputs the components s₁, . . . , s_(l) of the error syndromes, which is determined bys ₁ , . . . ,s _(l) =H·[y ₁ ′, . . . ,y _(k) ′,c ₁ ′, . . . ,c _(l) ′,A₁ ′, . . . ,A _(q)′]^(T)

If q=Q and A₁′, . . . , A_(q)=a₁′, . . . , a_(Q)′ then the syndrome isdetermined bys ₁ , . . . ,s _(l) =H·[y ₁ ′, . . . ,y _(k) c ₁ ′, . . . ,c _(l) ′,a ₁′, . . . ,a _(Q)′]^(T)wherein a₁′, . . . , a_(Q)′ is the complete read address.

If F(a₁′, . . . , a_(Q)′)=a₁′⊕ . . . , ⊕a_(Q)′=A₁′ applies, then thesyndrome depends on the parity of the components of the read address andthe following appliess ₁ , . . . ,s _(l) =H·[y ₁ ′, . . . ,y _(k) ′,c ₁ ′, . . . ,c _(l) ′,A₁′]^(T)

The syndrome generator 61 b comprises l first inputs to which thepossibly erroneous check bits c₁′, . . . , c_(l)′ are applied. Itcomprises k second inputs to which the possibly erroneous auxiliary readvalues y₁′, . . . , y_(k)′ apply and it comprises q further inputs towhich the outputs of the subcircuit F_(S) 63 for determining the bitsA₁′, . . . , A_(q)′ from the bits a₁′, . . . , a_(Q)′ of the readaddress a′ are connected. The subcircuit F_(S) is implemented so that itforms the bits A₁′, . . . , A_(q)′ from the bits of the read address a′.If, for example, Q=q and A₁′, . . . , A_(Q)′=a₁, . . . , a_(q), thesubcircuit F_(S) simply consists of q connecting lines which connect itsinputs to its outputs. If, for example, q=1 and A₁′=a₁′⊕ . . . ⊕a_(Q)′,then F_(S) is an XOR tree which outputs the parity of its input valuesat its output.

The subcircuit BB 19 is a combinational circuit. It forms, from thecorrected auxiliary read values y^(c)=y₁ ^(c), . . . , y_(k) ^(c), thecorrected input values x^(c)=x₁ ^(c), . . . , x_(k) ^(c). If no erroroccurs or if an error occurs which may be corrected by the code C, thenx^(c)=x.

Possible realizations of the subcircuit BB 19 are now to be explained inmore detail for different implementations of embodiments.

FIG. 7 a illustrates an embodiment of how the subcircuit BB 19 of FIG. 1d for 12 auxiliary read values y₁, . . . , y₁₂ and 9 binary input valuesx₁, . . . , x₉ may be implemented as a parallel circuit of thecombinational subcircuits BB₁ 71, BB₂ 72 and BB₃ 73, which realize thecombinational functions g₁, g₂ and g₃ each comprising 4 binary inputsand 3 binary outputs.

FIG. 8 serves for explaining how these subcircuits BB₁ 71, BB₂ 72 andBB₃ 73 may be determined.

In FIG. 8, a functional block diagram is illustrated, which serves forillustrating how the subcircuit BB 19 may be determined for anembodiment of a circuitry Cir₁ having 9 binary inputs x₁, x₂, . . . ,x₉.

In FIG. 8, as well as in FIG. 3 a, the subcircuit BT 11 with 9 binaryinputs is in turn realized from three subcircuits BT₁ 81 (31 in FIG. 3a), BT₂ 82 (32 in FIG. 3 a) and BT₃ 83 (33 in FIG. 3 a) which implementthe functions f₁, f₂ and f₃ each having three binary inputs and twoternary outputs, which carry the ternary state values z₁, . . . , z₆.These ternary state values z₁, . . . , z₆ are transformed by functionsLH¹ 84 . . . , LH⁶ 89 into the binary auxiliary read values y₁, . . . ,y₁₂. The functions LH¹ 84, . . . , LH⁶ 89 are the functions realized bythe subcircuit LH 16. The binary read values y₁, . . . , y₁₂ are now inturn transformed by the subcircuit BB 19 again into the binary inputvalues x₁, . . . , x₉. In this respect, three functions g₁, g₂ and g₃are determined each transforming back four binary auxiliary read valuesy₁, y₂, y₃, y₄; y₅, y₆, y₇, y₈ and y₉, y₁₀, y₁₁, y₁₂ into three binaryvalues x₁, x₂, x₃; x₄, x₅, x₆ and x₇, x₈, x₉, each. The subcircuit BB 19is a circuit which in turn includes the three subcircuits BB₁ 810 forrealizing the function g₁, BB₂ 811 for realizing the function g₂ and BB₃812 for realizing the function g₃.

First, the determination of function g₁ is considered. This function isdetermined from f₁, LH¹ and LH².

In the following tables, the values 0, 1 in columns designated by x_(i)or y_(i) designate binary values while the values 0, 1, 2 which are incolumns marked by z_(k) represent ternary values.

An embodiment is described, wherein function f₁ is given by table 1.

TABLE 1 (f₁(x₁, x₂, x₃)) x₁ x₂ x₃ z₁ z₂ 0 0 0 0 0 0 0 1 0 1 0 1 0 0 2 01 1 1 0 1 0 0 1 1 1 0 1 1 2 1 1 0 2 0 1 1 1 2 1

According to table 1, z₁, z₂ is simply a ternary representation of thevalues x₁ x₂ x₃ interpreted as a binary number.

The function LH¹ is described by table 2.

TABLE 2 (LH¹(z₁)) z₁ y₁ y₂ 0 0 0 1 0 1 2 1 1

The function LH² is described by table 3.

TABLE 3 (LH²(z₂)) z₂ y₃ y₄ 0 0 0 1 1 0 2 1 1

By now determining the ternary state values z₁, z₂ from the input valuesx₁, x₂, x₃ according to table 1, and subsequently determining, from thestate values z₁, z₂ according to table 2 and table 3, the correspondingauxiliary read values y₁, y₂, y₃, y₄, the auxiliary read values y₁, y₂,y₃, y₄ are determined from the input values x₁, x₂, x₃ by a functionk₁(x₁, x₂, x₃) as illustrated in table 4.

TABLE 4 (k₁(x₁, x₂, x₃)) x₁ x₂ x₃ y₁ y₂ y₃ y₄ 0 0 0 0 0 0 0 0 0 1 0 0 10 0 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 1 1 0 01 1 1 1 1 1 0

A description of function g₁ is now easily obtained from table 4 byregarding the output values y₁, y₂, y₃, y₄ of table 4 as input values ofthe function g₁, and by interpreting the associated input values x₁, x₂,x₃ of table 4 as output values of the function g₁. This way, table 5 isobtained which determines the function g₁ for the tupels of valuesindicated in table 5. For all values not indicated in table 5, thefunction g₁ may be determined randomly. This characteristic may be usedadvantageously for circuit optimization of the function g₁.

TABLE 5 (g₁(y₁, y₂, y₃, y₄)) y₁ y₂ y₃ y₄ x₁ x₂ x₃ 0 0 0 0 0 0 0 0 0 1 00 0 1 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 11 0 1 1 1 0 1 1 1

The subcircuit BB₁ 810 is now simply a combinational circuit forrealizing the function g₁ with 4 binary inputs y₁, y₂, y₃, y₄ and 3binary outputs x₁, x₂, x₃ whose functioning is determined by table 5,wherein the output values for values of y₁, y₂, y₃, y₄ not listed intable 5 may be selected randomly. For example, all of these outputvalues may be set to 0. The realization of a function given by a tableof values is no difficulty for a person skilled in the art, for exampleusing a synthesis tool and it is not to be described here in detail.

Now the determination of the function g₂ is considered. This function isdetermined from f₂, LH³ and LH⁴.

It is assumed that the function f₂ is given by table 6.

TABLE 6 (f₂(x₄, x₅, x₆)) x₄ x₅ x₆ z₃ z₄ 0 0 0 1 1 0 0 1 2 1 0 1 0 1 0 01 1 2 0 1 0 0 0 1 1 0 1 0 2 1 1 0 0 0 1 1 1 1 2

Function LH³ is described by table 7.

TABLE 7 (LH³(z₃)) z₃ y₅ y₆ 0 0 0 1 0 1 2 1 1

Function LH⁴ is described by table 8.

TABLE 8 (LH⁴(z₄)) z₄ y₇ y₈ 0 0 0 1 0 1 2 1 1

Here, LH³=LH⁴.

By now determining the ternary state values z₃, z₄ from the input valuesx₄, x₅, x₆ according to table 6 and subsequently determining thecorresponding auxiliary read values y₅, y₆, y₇, y₈ from the state valuesz₃, z₄ according to tables 7 and 8, the auxiliary read values y₅, y₆,y₇, y₈ are determined from the input values x₄, x₅, x₆ presented by afunction k₂(x₄, x₅, x₆) as in table 9.

TABLE 9 (k₂(x₄, x₅, x₆)) x₄ x₅ x₆ y₅ y₆ y₇ y₈ 0 0 0 0 1 0 1 0 0 1 1 1 01 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 0 0 01 1 1 0 1 1 1

A description of function g₂ is now simply obtained from table 9 byregarding the output values y₅, y₆, y₇, y₈ of table 9 as input values ofthe function g₂ and by interpreting the associated input values x₄, x₅,x₆ of table 9 as output values of the function g₂. This way, table 10 isobtained which describes the function g₂ for the values indicated intable 9. For all values not listed in table 10 the function g₂ may takeon arbitrary values. This characteristic may advantageously be used forcircuit optimization of the function g₂.

TABLE 10 (g₂(y₅, y₆, y₇, y₈)) y₅ y₆ y₇ y₈ x₄ x₅ x₆ 0 1 0 1 0 0 0 1 1 0 10 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 0 11 0 0 1 1 1 1 1 1

The subcircuit BB₂ 811 is now simply a combinational circuit forrealizing the function g₂ with four binary inputs y₅, y₆, y₇, y₈ andthree binary outputs x₄, x₅, x₆, whose functioning is determined bytable 10, wherein the output values for the occupations not listed intable 10 may be selected randomly by y₅, y₆, y₇, y₈. For example, all ofthese output values may be set equal to 0 or also equal to 1.

The subcircuit BB₃ 812 for realizing a function g₃ with four binaryinputs y₉, y₁₀, y₁₁, y₁₂ and three binary outputs x₇, x₈, x₉ may bedetermined completely analogously. It is for example also possible toselect the subcircuits BB₃ equal to the subcircuit BB₂ 811.

It is also possible to use equal subcircuits BB₁, BB₂ and BB₃ byselecting f₁=f₂=f₃ and LH¹=LH²= . . . =LH⁶ and determining one of thesubcircuits as described, like e.g. BB₂ and selecting the subcircuitsBB₁ and BB₃ equal to BB₂.

FIG. 3 b illustrates how the subcircuit BT 11 may be implemented with 11binary input values x₁, . . . , y₁₁ from subcircuits BT₁ 34 forrealizing a function f₁, BT₂ 35 for realizing a function f₂, BT₃, 36 forrealizing a function f₃ and BT₄ 37 for realizing a function f₄. Thesubcircuit for realizing the functions f₁, f₂ and f₃ each comprise threebinary inputs at which each three variable binary values x₁, x₂, x₃; x₄,x₅, x₆ and x₇, x₈, x₉ are applied. The subcircuit BT₄ for realizing thefunction f₄(x₁₀, x₁₁) comprises only two binary inputs at the inputs ofwhich variable values x₁₀ and x₁₁ are applied.

FIG. 7 b depicts the setup of subcircuit BB 19 from the subcircuits BB₁74 BB₂ 75, BB₃ 76 and BB₄ 77. The corresponding subcircuits BB₁, BB₂,BB₃ for realizing the functions g₁, g₂ and g₃ may be determined in acompletely analog way, like it was described for 9 input values x₁, . .. , x₉. The subcircuit BB₄ for realizing the function g₄(y₁₃, y₁₄, y₁₅,y₁₆) may simply be determined by determining a subcircuit for realizinga corresponding function g₄′ having three output variables and e.g.setting the third component constant, e.g. to 0.

For explanation purposes, the function g₄′(y₁₃, y₁₄, y₁₅, y₁₆)=g₂(y₁₃,y₁₄, y₁₅, y₁₆) with the output variables x₁₀, x₁₁, x₁₂ is used as it isillustrated in table 10 for the input variables y₅, y₆, y₇, y₈ and forthe output variables x₄, x₅, x₆. The following applies then

TABLE 11 (g′₄ (y₁₃, y₁₄, y₁₅, y₁₆)) y₁₃ y₁₄ y₁₅ y₁₆ x₁₀ x₁₁ x₁₂ 0 1 0 10 0 0 1 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 10 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1

(Table 11 for function g₄′ was determined completely analog like table10 for function g₂.)

By now selecting the lines of table 11 for which x₁₂=0, and by deletingall of the remaining lines and by deleting the column for x₁₂, table 12is acquired which describes the searched function g₄(y₁₃, y₁₄, y₁₅,y₁₆), which is realized by subcircuit BB₄.

TABLE 12 (g₄(y₁₃, y₁₄, y₁₅, y₁₆)) y₁₃ y₁₄ y₁₅ y₁₆ x₁₀ x₁₁ 0 1 0 1 0 0 01 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1

It is illustrated in FIG. 3 c how the subcircuit BT having 8 binaryinput values x₁, . . . , x₈ may be implemented from subcircuits BT₁ 38for realizing a function f, BT₂ 39 for realizing the same function f,BT₃ 310 for realizing a function φ and BT₄ 311 for realizing the samefunction φ. The subcircuits BT₁ 28 and BT₂ 29 for realizing the functionf each have three binary inputs and two ternary outputs, whilesubcircuits BT₃ 310 and BT₄ 311 each comprise a single binary input anda single ternary output for realizing the function φ.

The subcircuit BB 19, which realizes the corresponding subcircuits BB₁78, BB₂ 79, BB₃ 710 and BB₄ 711 are illustrated in FIG. 7 c. Thefollowing applies BB₁=BB₂ and BB₃=BB₄. The subcircuits BB₁ and BB₂ eachserve for realizing the function g, and the subcircuits BB₃ and BB₄ eachserve for realizing a function χ with a single binary input and a binaryoutput. Determining the function g may be done completely analogously asit was already described for functions g₁ or g₂ or for the subcircuit BB19 of FIG. 7 a and is thus not to be explained again.

One advantageous implementation of the subcircuit BB₃ 710 which realizesthe function χ is now to be described.

In FIG. 3 c, the subcircuit BT₃ 310 forms the binary value x₇ into theternary value z₅. In one embodiment, the following may apply for theassociated function φ:φ(0_(bin))=0_(ter) and φ(1_(bin))=2_(ter).

If now the subcircuit LH⁵ 165 in FIG. 4 for m=4 and M=6 is implementedfor determining the auxiliary read values LH⁵(z₅) so thatLH ⁵(0_(ter))=0_(bin) ,LH ⁵(1_(tern))=LH ⁵(2_(ter))=1_(bin),then χ(0)=0 and χ(1)=1, and the subcircuit for realizing the function χthen simply consists of a connecting line.

The considered implementation is error-tolerant for memory errors inwhich a ternary value z₅=2_(tern) stored in the memory is corrupted intoa ternary value z₅′=1_(ter). A binary value 1 which was written into theternary memory as a ternary value 2_(ter) is read out as a binary value1_(bin) independent of whether the ternary value 2_(ter) in the memorySp 13 erroneously was corrupted into the ternary value 1_(ter) or not.Likewise it is possible to store the binary value x₇ as a binary valueunchanged as z₅=x₇ into the memory Sp 13. In this case it is alsopossible to use binary memory cells for storing z₅ and z₆, while theternary values z₁, . . . , z_(m) with m=4 are stored in the memory cellswith ternary state values.

Advantageously, the memory Sp 13 may comprise a ternary partial memorySp_(ter) 131 and a binary partial memory Sp_(bin) 132, as it isillustrated in FIG. 1 f, wherein the binary check bits c₁, . . . , c_(l)are stored as binary values in a binary partial memory Sp_(bin) 122,while the ternary state values z₁, . . . , z_(m) and the state valuesz_(m+1), . . . , z_(M) are stored in a ternary partial memory Sp_(ter).

Storing the check bits c₁, . . . , c_(l) generated by the coder Cod 12in the memory Sp 13 and reading out the stored check bits from thememory Sp 13 is now to be explained again in more detail when the memorycells Spc₁, . . . , Spc_(l) are either ternary memory cells or binarymemory cells.

First of all the case is described that these memory cells are ternarymemory cells and may take on three different states. In order to avoidconfusion, here, the ternary values are designated by 0_(ter), 1_(ter)and 2_(ter) and the binary values are designated by 0_(bin), 1_(bin).

For j=1, . . . , l, the binary check bit c_(j) output at the j-th outputof the encoder Cod 12 is applied to the input of the subcircuit bt_(j)14 j with a binary input and a ternary output. The subcircuit bt_(j) 14j outputs a ternary value bt_(j)(c_(j))=c_(j)′ at its output.

In one embodiment, the subcircuit bt_(j)(c_(j)) is determined so thatthe following appliesc _(j) ^(t) =bt _(j)(c _(j)) with bt _(j)(0_(bin))=0_(ter) and bt_(j)(1_(bin))=2_(ter).

The subcircuits tb₁, . . . , tb_(l) 15 j transform the possiblyerroneous ternary values c₁ ^(t′), . . . , c_(l) ^(t′) read out from thememory component after component into binary values c₁′=tb₁(c₁ ^(t′)), .. . , c_(l)′=tb_(l)(c_(l) ^(t′)) so that for j=1, . . . , l, thefollowing applies:c _(j) ′=tb _(j)(c _(j) ^(t′)) with tb _(j)(0_(ter))=0_(bin) and tb_(j)(1_(ter))=tb _(j)(2_(ter))=1_(bin).

If a ternary value 2 is corrupted into a ternary value 1 in memory cellsof the ternary memory Sp 13 in which values c_(j)′, . . . , c_(l)′ werewritten, this error has no effect at the corresponding output of thesubcircuit TrTB 16, as by the function tb_(j) both the ternary value2_(ter) and also the ternary value 1_(ter) are mapped into the binaryvalue 1_(bin). This is advantageous.

If the memory cells Spc₁, . . . , Spc_(l) are binary memory cells, thenboth the subcircuits bt₁, 141, . . . , bt_(l) 14 l and also thesubcircuits tb₁ 151, . . . , tb_(l) 151 may be realized as a connectionof their inputs to their respective outputs. The check bits c₁, . . .c_(l) output by the coder Cod 12 are then written binarily into thememory cells Spc₁, . . . , Spc_(l) and read out as binary possiblyerroneous check bits c₁′, . . . , c_(l)′ which are provided at thecorresponding inputs of the corrector Cor 17.

In the following, now, a special implementation of the corrector Cor 17is to be explained which is illustrated in FIG. 1 g. In FIG. 1 g, thespecial implementation of the corrector Cor is designated by 17 c. Thecorrector Cor 17 c comprises l first inputs for inputting the possiblyerroneous check bits c₁′, . . . , c_(l)′, k second inputs for inputtingthe possibly erroneous auxiliary read values y₁′, . . . , y_(k)′ and qfurther inputs for inputting the bits A₁′, . . . , A_(q)′=F(a₁′, . . . ,a_(Q)′) which were formed from the bits a₁′, . . . , a_(Q) of the readaddress a′=a₁′, . . . , a_(Q). The corrector Cor 17 c also comprises kfirst outputs for outputting a correction vector e=e₁, . . . , e_(k) forcorrecting the auxiliary read values y₁′, . . . , y_(k)′ and q furtheroutputs for outputting a correction vector e^(A)=e₁ ^(A), . . . , e_(q)^(A) for correcting the bits A₁′, . . . , A_(q)′ derived from theaddress bits.

The q outputs which carry the component of the correction vector e^(A)are connected to the q inputs of an OR circuit 121 c having q inputs andto a single output, wherein the output outputs the error signal E_(A)when at least one bit of the correction vector e^(A) is equal to 1,which indicates an error in the read address a′.

If E_(A)=1, then the read address a′ is different from the write addressa, so that data is not valid.

If q=Q and a₁′, . . . , a_(Q)′=A₁′, . . . , A_(q)′, then it is indicatedby the correction vector e^(A) for each address bit whether there is anerror in this bit. If the corrector, as described in FIG. 6 b,determines an error syndrome, an error message may be generated for anaddress error when the error syndrome corresponds to an address error.

It is also possible to implement the corrector so that in addition tothe correction bits e₁, . . . , e_(k), e_(a1), . . . , e_(kQ) forcorrecting the auxiliary read values and the address bits it alsogenerates correction values e₁ ^(c), . . . , e_(l) ^(c) of the checkbits.

According to an embodiment, a circuitry for storing binary data x₁, . .. , x_(n) and for error correction with a binary code C is provided, thecomprising the following features:

1. A ternary memory circuitry 13 h exists, comprising a ternary memorySp 13 with ternary memory cells, wherein the binary data x₁, . . . x_(n)are written in memory cells having three states at a write address a₁, .. . , a_(Q) as encoded ternary states z₁, . . . , z_(M), and wherein acoder 12 h writes certain binary check bits c₁, . . . , c_(l) in memorycells, and wherein, when the check bits c₁, . . . , c_(l) are check bitsof the data bits x₁, . . . , x_(n) which are written at write addressa₁, . . . , a_(Q), the check bits are also written at the same writeaddress of the corresponding data bits, and wherein, when reading at aread address a₁′, . . . , a_(Q)′ of memory cells of the ternary memory,which are adapted to take on three different values, possibly erroneousstate values z₁′, . . . , z_(M)′ are output which are transformed intopossibly erroneous binary auxiliary read values y₁′, . . . , y_(k)′, andwherein, furthermore, possibly erroneous check bits c₁′, . . . c_(l)′are output, and wherein, when the write address is equal to the readaddress and when no error is present, error-free auxiliary read valuesy₁, . . . , y_(k) and error-free check bits c₁, . . . , c_(l) areoutput,2. A coder Cod 12 h exists comprising a first n-bit wide first input forinput of data bits x₁, . . . , x_(n) and a further q-bit wide input forinput of bits A₁, . . . , A_(q) and an l-bit wide output for output ofcheck bits c₁, . . . , c_(l), wherein the bits A₁, . . . , A_(q) aredetermined based on the bits of the write address a₁, . . . , a_(Q),wherein the data bits x₁, . . . , x_(n), and the corresponding checkbits are written under said write address a₁, . . . , a_(Q), wherein thecoder is configured such that the check bits c₁, . . . , c_(l) aredetermined from the data bits x₁, . . . , x_(n) and the bits A₁, . . . ,A_(q), so thaty ₁ , . . . ,y _(k) , A ₁ , . . . ,A _(q) , c ₁ , . . . ,c _(l)is a codeword of the error-correcting code C, and wherein the bits A₁, .. . , A_(q) are uniquely determined from the bits of the write addressa₁, . . . , a_(Q), so that the bits A₁, . . . , A_(q) are output valuesof a combinational circuitry F with Q binary inputs and q binaryoutputs, when the write address a₁, . . . , a_(Q) is fed into the inputsof said circuitry, wherein q≦Q applies.

According to a particular embodiment, q=Q, and a₁, . . . , a_(Q)=A₁, . .. , A_(Q).

In another particular embodiment, A₁=a₁⊕ . . . ⊕a_(Q).

According to a further embodiment, the code C is a linear code.

In another particular embodiment, the Code C is a linear code with agenerator matrix G=(l, P), and wherein l is a (k+q)-identity matrix, andwherein P is a [(k+q), l]-parity matrix, and wherein the check bits c₁,. . . c_(l) are defined byc ₁ , . . . ,c _(l)=(y ₁ , . . . ,y _(k) ,A _(a) , . . . ,A _(Q))·P

FIG. 1 h illustrates an embodiment, wherein data bits are stored inmemory cells of a ternary memory circuitry 13 h, wherein the memorycells of the ternary memory are configured to take on (one of) threedifferent states. The write and read addresses of the ternary memory ofthe ternary memory circuitry are employed for error handling, e.g. forerror detection and/or error correction.

The ternary memory circuitry 13 h comprises memory cells, in which databits can be stored as ternary states.

When writing, input values x₁, . . . , x_(n) on the n-bit wide inputline 110 g are input into the ternary memory circuitry 13 h, and checkbits c₁, . . . , c_(l) on the l-bit wide input line 111 g are input intothe ternary memory circuitry 13 h. Write address a₁, . . . , a_(Q) isfed into the Q-bit wide address input line 115 h when writing. Whenreading, read address a₁′, . . . , a_(Q)′ is fed into the Q-bit wideinput line 115 h. When reading, binary auxiliary read values y₁′, . . ., y_(k)′ are output on the k bit wide output line 112 g, and check bitsc₁′, . . . , c_(l)′ are output on the l bit wide output line 113 h.

The input line 110 g is moreover connected to a first n-bit wide inputof coder Cod 12 h. Bits A₁, . . . , A_(q) are input at a q bit widesecond input of the coder Cod 12 h. The bits A₁, . . . , A_(q) aregenerated by a combinational circuitry F_(S) 56 h at the write addressa₁, . . . , a_(Q) according toA ₁ , . . . ,Aq=F(a ₁ , . . . ,a _(Q)),wherein F is a unique mapping of the Q address bits a₁, . . . , a_(Q) tothe bits A₁, . . . , A_(q) which are derived from the address bits asalready explained above.

The k-bit wide output line 112 g, which carries the possibly erroneousauxiliary read values y₁′, . . . , y_(k)′, is connected to a first k-bitwide input of a combinational circuitry 18 h and is also connected to afirst k-bit wide input of a corrector Kor 17 h. An output line 113 h isconnected to a second l-bit wide input of the corrector Kor 17 h,wherein the output line 113 h carries the possibly erroneous check bitsc₁′, . . . , c_(l)′. A q-bit wide output of the circuitry 55 h isconnected to the third q-bit wide input of the corrector Kor 17 h,wherein a q-bit wide value A₁′, . . . , A_(q)′ is output on the q-bitwide output of the circuitry 55 h. A binary read address a₁′, . . . ,a_(Q)′ is fed into the circuitry F_(S) 55 at a Q-bit wide input of thecircuitry F_(S) 55 h.

The functionality of the circuitry F_(S) 55 h is equal to thefunctionality of the circuitry F_(S) 56 h, which is the reason forgiving both circuitry 55 h as well as circuitry 56 h the name “F_(S)”.

The corrector Kor 17 h outputs the correction vector e₁, . . . , e_(k)at its k-bit wide output, which is connected to the second input of thecombinational circuitry 18 h, which is a correction circuitry. In FIG. 1h, the correction circuitry is implemented as an XOR circuitry. In otherembodiments, other implementations may be realized, such as e.g.employing a XNOR circuitry.

In the embodiment of FIG. 1 h, the XOR circuitry 18 h outputs at itsk-bit wide output the corrected auxiliary read valuesy ^(cor) =y ₁ ^(cor) , . . . ,y _(k) ^(cor) =y ₁ ′⊕e ₁ , . . . ,y _(k)′⊕e _(k)which are transformed into corrected data values x^(cor)=x₁ ^(cor) . . .x_(n) ^(cor) by a combinational circuitry BB 19 h.

If a₁, . . . , a_(Q)=a₁′, . . . , a_(Q)′ applies, so that the writeaddress is equal to the read address, and if no error is present in theternary memory circuitry 13 h, the coder 12 h and the circuitry F_(S) 56h, then the auxiliary read values being output on line 112 g arereferred to as correct auxiliary read values y₁, . . . , y_(k).

The possibly erroneous check bits c₁′, . . . , c_(l)′ which are outputon output line 113 h are defined by the check bits c₁, . . . , c_(l).Those check bits c₁, . . . , c_(l) are output at output 111 g of Coder12 h, are stored at write address a₁, . . . , a_(Q) in memory cells ofthe ternary memory circuitry 13 h and are read out at read address a₁′,. . . , a_(Q)′. The check bits may be stored in memory cells which maytake on one of three different states as well as in memory cells whichmay take on one of two different states.

The Coder Cod 12 h is configured such that it generates the check bitsc₁, . . . , c_(l) such thaty ₁ , . . . ,y _(k) , A ₁ , . . . ,A _(q) ,c ₁ , . . . ,c _(l)is a codeword of an error-correcting code C.

If the code C is a linear code with a generator matrix G=(l, P), whereinl is a (k+q)-identity matrix, and wherein P is a [(k+q), l]-paritymatrix, then c₁, . . . , c_(l) may be determined asc ₁ , . . . ,c _(l)=(y ₁ , . . . ,y _(k) ,A _(a) , . . . ,A _(Q))·P.

The corrector Kor 17 h outputs a correction vector e=e₁, . . . , e_(k),so thaty ^(cor) =y ₁ ^(cor) , . . . ,y _(k) ^(cor) =y ₁ ′⊕e ₁ , . . . ,y _(k)′⊕e _(k) =y ₁ , . . . ,y _(k)applies, when errors which did occur are correctable by theerror-correcting code C.

If the code C is, for example, a 1-bit error-correcting code, then eachsingle bit error, for example, in the auxiliary read values or in thecheck bits can be validly corrected. If the code C is a 2-biterror-correcting code, then each 2-bit error in the auxiliary readvalues or in the check bits can be corrected.

A first specific embodiment of the ternary memory circuitry 13 h of FIG.1 h is illustrated by FIG. 1 i.

The ternary memory circuitry 13 h comprises a subcircuit BT 11 fortransforming the binary data bits x₁, . . . , x_(n) into state valuesz₁, . . . , z_(M) to be stored in memory cells of ternary memory Sp 13,wherein the ternary memory Sp 13 comprises memory cells having ternarystate values and wherein the ternary memory Sp 13 comprises memory cellsSpc₁, . . . , Spc_(l), with at least two states for storing binary checkbits c₁, . . . , c_(l), and a subcircuit LH 16 for transforming possiblyerroneous ternary state values z₁′, . . . , z_(M)′, being read out fromthe memory Sp 13, into binary auxiliary read values y₁′, . . . , y_(k)′.It is possible that the memory cells Spc₁, . . . , Spc_(l) are binarymemory cells.

The data bits x₁, . . . , x_(n) are input at the n-bit wide input line110 h. The possibly erroneous auxiliary read values y₁′, . . . , y_(k)′are output on a k-bit wide output line 112 h. The possibly erroneouscheck bits c₁′, . . . , c_(l)′ are output on an l-bit wide output line113 h. As the subcircuits BT 11, Sp 13 and LH 16 have already beendescribed with reference to FIG. 1 a, they will be not explained onceagain.

A second specific embodiment of the ternary memory circuitry 13 h ofFIG. 1 h is illustrated by FIG. 1 j. The ternary memory circuitry inFIG. 1 j comprises a subcircuit BT 11 for transforming the binary databits in state values z₁, . . . , z_(M), a memory Sp 13, which herecomprises ternary memory cells Spc₁, . . . , Spc_(l) for storing thecheck bits, wherein the check bits c₁, . . . , c_(l) are transformed bysubcircuits bt₁ 141, . . . , bt_(l) 14 l into ternary values c₁ ^(t), .. . , c_(l) ^(t), a subcircuit LH 16 for transforming possibly erroneousstate values z₁′, . . . , z_(M)′, being read out from the memory Sp 13into possibly erroneous auxiliary read values y₁′, . . . , y_(k)′, andsubcircuits tb₁ 151, . . . , tb_(l) 15 l for transforming the possiblyerroneous check bits, being read out from the memory cells Spc₁, . . . ,Spc_(l).

The data bits x₁, . . . , x_(n) are input at an n-bit wide input line110 h. The check bits c₁, . . . , c_(l) are input at the l-bit wideinput line 111 h. The possibly erroneous auxiliary read values y₁′, . .. , y_(k)′ are output at the k-bit wide output line 112 h. The possiblyerroneous check bits c₁′, . . . , c_(l)′ are output at the l-bit wideoutput line 113 h. The employed subcircuits have already been describedwith reference to FIGS. 1 a and 1 d and will not be described onceagain.

A further specific embodiment of the ternary memory circuitry 13 h ofFIG. 1 h is illustrated by FIG. 1 k. The ternary memory circuitry inFIG. 1 k comprises a subcircuit BT 11 k for transforming the binary databits and the binary check bits into state values z₁, . . . , z_(M′),which may take on one of three different values, a ternary memory Sp 13,which here, e.g., only comprises ternary memory cells, a subcircuit LH16 k for transforming the possibly erroneous state values z₁′, . . . ,z_(M)′, into possibly erroneous auxiliary read values y₁′, . . . ,y_(k)′, y_(k+m)′, . . . , y_(K)′, and a subcircuit BB 19 k fortransforming the auxiliary read values y_(k+m)′, . . . , y_(K)′ intopossibly erroneous check bits c₁′, . . . , c_(l)′. In this embodiment,it is possible that a triple of binary data bits as well as a triple ofbinary check bits are each stored as a tuple of ternary values in twomemory cells of the memory 13 k. The data bits x₁, . . . , x_(n) areinput at the n-bit wide input line 110 h. The check bits c₁, . . . ,c_(l) are input at the l-bit wide input line 111 h. The possiblyerroneous auxiliary read values y₁′, . . . , y_(k)′ are output at thek-bit wide output line 112 h. The possibly erroneous check bits c₁′, . .. , c_(l)′ are output at the l-bit wide output line 113 h.

As the subcircuit BT 11 k transforms the data bits x₁, . . . , x_(n) aswell as the check bits, being output by the coder Cod 12 h, into ternarystate values z₁, . . . , z_(M′), the input word width of the subcircuitBT 11 k is here n+l. The auxiliary read values y₁′, . . . , y_(k)′ beingoutput by the subcircuit LH 16 k correspond to the data bits x₁′, . . ., x_(n)′, while the auxiliary read values y_(k+m)′, . . . , y_(K)′ areassigned to the check bits c₁′, . . . , c_(l)′.

Except of the input word widths and the output word widths, the employedsubcircuits correspond to the subcircuits already described.

The employed subcircuits have already been described, in particular withreference to FIG. 1 a, and are therefore not described once again.

Now a further realization possibility for the subcircuit BT 11 is to bedescribed.

The subcircuit BT 11 may be realized as a series connection of asubcircuit BBS 94 for the transformation of binary input values x₁, . .. , x_(n) into binary auxiliary write values y₁ ^(s), . . . , y_(k) ^(s)and of a subcircuit BTS 95 which transforms the binary auxiliary writevalues y₁ ^(s), . . . , y_(k) ^(s) into the state values z₁, . . . ,z_(m), z_(m+1), . . . , z_(M) as it is illustrated in FIG. 9 b.

As it is illustrated in FIGS. 3 a, 3 b and 3 c, the subcircuit BT 11 mayin turn be setup from subcircuits BT_(j) j=1, 2, . . . . As an example,again the realization of the subcircuit BT₂ 32 is to be described whichconverts the binary input values x₄, x₅, x₆ into ternary state valuesz₃, and z₄ according to table 6. Its currently considered implementationis illustrated in FIG. 9 a. The described conversion of the binary inputvalues x₄, x₅, x₆ into ternary state values in the illustrative exampleis executed in two steps. In a first step the three binary input valuesx₄, x₅, x₆ are transformed into four binary auxiliary write values y₅^(S), y₆ ^(S), y₇ ^(S), y₈ ^(S) withy ₅ ^(S) ,y ₆ ^(S) ,y ₇ ^(S) ,y ₈ ^(S) =k ₂(x ₄ ,x ₅ ,x ₆).

In a second step, a ternary state is assigned to the first pair y₅ ^(S),y₆ ^(S), and to the second pair y₇ ^(S), y₈ ^(S) of the four binaryauxiliary write values.

There are only eight different input values x₄, x₅, x₆ and thus onlyeight different 4-tuples of auxiliary write values y₅ ^(S), y₆ ^(S), y₇^(S), y₈ ^(S). The transformation of the triple of the input values x₄,x₅, x₆ into the auxiliary write values is executed, so that each of thetwo tuples y₅ ^(S), y₆ ^(S) and y₇ ^(S), y₈ ^(S) takes on only threedifferent values and may thus in a second step be encoded and stored asa ternary state. Here, k₂ is a combinational function with three binaryinput variables x₄, x₅, x₆ and four binary output variables y₅ ^(S), y₆^(S), y₇ ^(S), y₈ ^(S).

In a second step the first pair y₅ ^(S), y₆ ^(S) of the binary auxiliarywrite values is transformed by a function q₃ with two binary inputvariables y₅ ^(S), y₆ ^(S) and a ternary output variable z₃ into a firstternary state z₃, while the second pair y₇ ^(S), y₈ ^(S) of binaryauxiliary write values is transformed by a function q₄ with two binaryinput variables and a ternary output variable into a second ternarystate z₄. The functions q₃ and q₄ may here be selected equal to eachother or different from each other.

The function q₃ describes a digital to analog conversion of the digitalbinary values y₅ ^(S), y₆ ^(S) into an analog value, which depending onthe assignment to one of three non-overlapping intervals represents oneof the three possible ternary values of z₃. Accordingly, the function q₄describes a digital to analog conversion of the digital values y₇, y₈into an analog value, which represents one of the possible ternaryvalues of z₄.

The described transformation may be realized by a subcircuit Sk₂ 91 withthree binary inputs and four binary outputs for realizing the functionk₂ and two downstream subcircuits Sq₃ 92 and Sq₄ 93 for realizing thefunctions q₃ and q₄, as illustrated in FIG. 9 a.

At the 3-bit wide input of the subcircuit Sk₂ 91, the value x₄, x₅, x₆is applied. The first two binary outputs of the subcircuit Sk₂ 91 whichcarry the auxiliary write values y₅ ^(S), y₆ ^(S) are fed into the 2-bitwide binary input of the subcircuit Sq₃ 92, while the second binaryoutputs of the subcircuit Sk₂ 91, which carry the auxiliary write valuesy₇ ^(S), y₈ ^(S) are fed into the 2-bit wide binary input of thesubcircuit Sq₄ 93. The subcircuit Sq₃ 92 outputs the value z₃ at itsternary output, while the subcircuit Sq₄ 93 outputs the value z₄ at itsternary output.

It is possible that the auxiliary write values y₅ ^(S), y₆ ^(S), y₇^(S), y₈ ^(S) are functionally determined from the input values x₄, x₅,x₆, just like the auxiliary read values y₅ ^(S), y₆ ^(S), y₇ ^(S), y₈^(S) are determined from the input values x₄, x₅, x₆, and they are equalin the error-free case, as, for example, described in table 9.

It is not necessary that for all input values, here for the 8 possiblevalues of x₄, x₅, x₆, the auxiliary write values determined from x₄, x₅,x₆ are equal to the auxiliary read values also determined from x₄, x₅,x₆.

It may be practical, however, to use such auxiliary write values whenstoring, which are used as auxiliary read values, when reading out, asit will be explained in more detail later.

As an example, here, the case of 8 data bits x₁, . . . , x₈ isconsidered, and the use of the auxiliary write values is explained alsofor determining the check bits for an advantageous implementation of theencoder 12, when the auxiliary write values are equal to the auxiliaryread values. It is, for example, assumed that the two triples x₁, x₂, x₃and x₄, x₅, x₆ are converted into auxiliary write values y₁ ^(S), y₂^(S), y₃ ^(S), y₄ ^(S), and y₅ ^(S), y₆ ^(S), y₇ ^(S), y₈ ^(S) in thesame way as it is illustrated in FIG. 10.

The bits x₁, x₂, x₃ are transformed into the auxiliary read values y₁^(S), y₂ ^(S), y₃ ^(S), y₄ ^(S) by the subcircuit Sk₂ 101, while thebits x₄, x₅, x₆ are transformed into the auxiliary read values y₅ ^(S),y₆ ^(S), y₇ ^(S), y₈ ^(S) by the subcircuit Sk₂ 102. The two bits x₇ andx₈ are directly used as auxiliary write values y₉ ^(S), and y₁₀ ^(S).

The pairs of auxiliary write values [y₁ ^(S), y₂ ^(S)], [y₃ ^(S), y₄^(S)], [y₅ ^(S), y₆ ^(S)], [y₇ ^(S), y₈ ^(S)] are transformed by thesubcircuits Sk₃ 103 Sk₄ 104 Sk₃ 105 Sk₄ 106 into the ternary states z₁,z₂, z₃, z₄, which are stored in the memory Sp 1013. The auxiliary readvalue y₉ ^(S)=x₇ is transformed into the ternary state z₅ by thesubcircuit bt₇ 107. The auxiliary read value y₁₀ ^(S)=x₈ is transformedinto the ternary state z₆ by the subcircuit bt₅ 108. The states z₅ andz₆ are also stored in the ternary memory Sp 1013.

The auxiliary write values y₁ ^(S), . . . , y₁₀ ^(S) are also applied to10 first inputs of the subcircuit Bincode 109, at whose second q inputsthe bits A₁, . . . , A_(q) derived from the read address a, . . . ,a_(Q) are applied. In this embodiment, the subcircuit Bincode 109outputs 5 check bits c₁, . . . , c₅ which are transformed by thesubcircuit bt₁ 1010, . . . , bt₅ 1011 into the ternary values c₁′, . . ., c₅′, which are each stored in separate memory cells Spc₁, . . . , Spc₅of the memory Sp 1013.

The subcircuit BT 11 here in turn includes the subcircuits Sk₂ 101, Sk₂102, the subcircuits Sk₃ 103, Sk₄ 104, Sk₃ 105, Sk₄ 106, bt₇ 107 and bt₈108.

The coder Cod 12 is setup from the subcircuits Sk₂ 101, Sk₂ 102 and thesubcircuit Bincode 109. The subcircuit BT and the coder Cod 12 are herejointly implemented.

The conversion of the bits x₄, x₅, x₆ into the auxiliary write values y₅^(S), y₆ ^(S), y₇ ^(S), y₈ ^(S) is considered in detail, wherein theauxiliary read values used when reading are equal to the auxiliary writevalues used when writing, so that when no error occurred, [y₅, y₆, y₇,y₈]=[y₅ ^(S), y₆ ^(S), y₇ ^(S), y₈ ^(S)] applies.

When reading, the conversion of the ternary state values read out fromthe two associated memory cells into corresponding binary auxiliary readvalues for the memory cell in which the state value z₃ is stored, is tobe executed by the function LH³ illustrated in table 7, and for thememory cell in which the state value z₄ is stored is to be executed bythe function LH⁴ illustrated in table 8.

It is illustrated in table 9, how corresponding binary auxiliary readvalues y₅, y₆, y₇, y₈ are assigned to the binary input values x₄, x₅,x₆. For example, as already stated above, for all value combinations ofx₄, x₅, x₆ which are not listed in table 9, y₅=y₆=y₇=y₈=0 may be set.The assignment by table 9 is described by the function k₂(x₄, x₅, x₆).It is no difficulty for a person skilled in the art to determine acombinational circuit Sk₂ from table 9 which realizes the function k₂.

It is assumed here that the auxiliary write values y₅ ^(S), y₆ ^(S), y₇^(S), y₈ ^(S) are determined by the same function k₂ as the auxiliaryread values, so that the subcircuit Sk₂ 91 is simply a combinationalcircuit Sk₂, which realizes the function k₂ described in table 9.

From the pairs y₅, y₆ and y₇, y₈, which are equal to the correspondingpairs of auxiliary read values or auxiliary write values, then, theternary state values z₃ and z₄ are determined by functions q₃ and q₄according to tables 13 and 14, wherein the ternary state values z₃ andz₄ are stored into the ternary memory Sp 13. Here, the possible statevalues of z₃ are designated as A₀, A₁, A₂ and the possible state valuesof z₄ are designated as B₀, B₁, B₂.

Table 13 describes the function q₃ and table 14 describes the functionq₄.

TABLE 13 q₃(y₅, y₆) y₅ y₆ z₃ 0 0 0 0 1 1 1 1 2 1 0 —

TABLE 14 q₄(y₇, y₈) y₇ y₈ z₄ 0 0 0 1 0 1 1 1 2 0 1 —

As before, the columns of tables 13 and 14, marked by y_(i), comprisebinary values and the columns marked by z_(j) comprise ternary values.The functions q₃ and q₄ are realized by circuits Sq₃ and Sq₄, whichexecute a digital to analog conversion, and whose realization by ananalog to digital converter is no difficulty for a person skilled in theart.

The realization of the coder Cod 12 and the corrector Cor 17 is now tobe explained for a special embodiment for a special linear code, whereineight binary input values x₁, . . . , x₈ are to be stored. These eightbinary input values, as described above, are transformed into 10 binaryauxiliary read values y₁, . . . , y₁₀, which represent the data orinformation bits of the linear code C. The code C comprises 10information bits y₁, . . . , y₁₀ and 5 check bits c₁, . . . , c₅. Thecode C may be described by a (10, 15)-G-matrix G and by a (5,15)-H-matrix H. As an example of a generator matrix, the followinggenerator matrix G is chosen.

$\begin{matrix}{G = \begin{pmatrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 \\0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 0 \\0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 1\end{pmatrix}} & (1)\end{matrix}$

The G-matrix has the following formG=(I ₁₀ ,P _(10,5)).  (2)

Here, l₁₀ is the 10-dimensional identity matrix and P_(10,5) with

$\begin{matrix}{P_{10,5} = \begin{pmatrix}1 & 1 & 1 & 0 & 0 \\1 & 1 & 0 & 1 & 0 \\1 & 1 & 0 & 0 & 1 \\1 & 0 & 1 & 1 & 0 \\1 & 0 & 1 & 0 & 1 \\1 & 0 & 0 & 1 & 1 \\0 & 1 & 1 & 1 & 0 \\0 & 1 & 1 & 0 & 1 \\0 & 1 & 0 & 1 & 1 \\0 & 0 & 1 & 1 & 1\end{pmatrix}} & (3)\end{matrix}$is the parity matrix.

The check bits c₁, . . . , c₅ are determined byc ₁ ,c ₂ ,c ₃ ,c ₄ ,c ₅=(y ₁ ,y ₂ ,y ₃ ,y ₄ ,y ₅ ,y ₆ ,y ₇ ,y ₈ ,y ₉ ,y₁₀)·P _(10,5)  (4)so thatc ₁ =y ₁ ⊕y ₂ ⊕y ₃ ⊕y ₄ ⊕y ₅ ⊕y ₆c ₂ =y ₁ ⊕y ₂ ⊕y ₃ ⊕y ₇ ⊕y ₈ ⊕y ₉c ₃ =y ₁ ⊕y ₄ ⊕y ₅ ⊕y ₇ ⊕y ₈ ⊕y ₁₀c ₄ =y ₂ ⊕y ₄ ⊕y ₆ ⊕y ₇ ⊕y ₉ ⊕y ₁₀c ₅ =y ₃ ⊕y ₅ ⊕y ₆ ⊕y ₈ ⊕y ₉ ⊕y ₁₀being realized by the subcircuit Bincode 109 in FIG. 10. In this specialexample C is a binary code and as a special case the circuit Bincodeimplements the check-bit generation of the code C. A person skilled inthe art understands that the considered code C is a Hsiao code which maycorrect all 1-bit errors and detect all 2-bit errors.

The implementation of the check bits c₁, . . . , c₅ determined from theauxiliary read values y₁, . . . , y₁₀ by XOR operations is not adifficulty for a person skilled in the art and is thus not to beexplained in more detail.

The pairs [y₁, y₂], [y₃, y₄], [y₅, y₆], [y₇, y₈], . . . , of auxiliaryread values which are each derived from a ternary state value stored ina ternary memory cell each only take on three different values, e.g. thevalues [0,0], [0,1], [1,1]. Pairs of check bits, however, take on fourdifferent values, which is why a pair of check bits may not be stored ina ternary memory cell. This is to be explained for the pair [c₁, c₂] ofcheck bits.

If all auxiliary read values are equal 0, y₁=y₂= . . . =y₁₀=0, then [c₁,c₂]=[0, 0].

If [y₁, y₂]=[0, 1] and if all other auxiliary read values are equal to0, then [c₁, c₂]=[1, 1].

If [y₃, y₄]=[1, 1] and if all other auxiliary read values are equal to0, then [c₁, c₂]=[0, 1].

If [y₁. y₂]=[0, 1] and if [y₃, y₄]=[1, 1] and if all other auxiliaryread values are equal to 0, then [c₁, c₂]=[1, 0].

A pair of check bits may thus not be stored in one single ternary memorycell.

In the following, one possible implementation of the corrector Corr willnow be described for the considered linear code C. The error correctionis executed so that from the read out possible erroneous memory statesz₁′, . . . , z₈′, the auxiliary read values y₁′, . . . , y₁₀′ areformed, as described, and then these auxiliary read values and thepossibly erroneous check bits c₁′, . . . , c₅′ by the corrector Korr1016 the correction vector e=e₁, . . . , e₁₀ is determined.

The error correction is executed using the H-matrix H of the code Cwhich is as known determined to be H=(P_(5,10) ^(T), l₅)=(h₁, . . . ,h₁₅), wherein P_(5,10) ^(T) is the transposed matrix of the matrixP_(10,5) in which lines and columns are exchanged and l₅ is the5-dimensional identity matrix, so that

$\begin{matrix}{H = \begin{pmatrix}1 & 1 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 \\1 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1\end{pmatrix}} & (5)\end{matrix}$applies. Here, h_(i) for i=1, . . . , 15 are the columns of the H-matrixH.

All columns of the H-matrix H are different and each column h_(i), i=1,. . . , 15 either contains one 1 or three 1s, i.e. an odd number ofones.

As illustrated by FIG. 6 a, the corrector 17 a comprises a syndromegenerator 61 a which for k=10 and l=5 comprises the possible erroneousauxiliary read values y₁′, . . . , y₁₀′ and the possibly erroneous checkbits c₁′, . . . , c₅′ read out from the memory according to thefollowing relations=[s ₁ , . . . ,s ₅]^(T) =H·[y ₁ ′, . . . ,y ₁₀ ′,c ₁ ′, . . . ,c₅′]^(T)  (6)form an error syndrome s, as it is conventional for a linear code sothat the individual components s₁, . . . , s₅ of the error syndrome aredetermined to bes ₁ =c ₁ ′⊕y ₁ ′⊕y ₂ ′⊕y ₃ ′⊕y ₄ ′⊕y ₅ ′⊕y ₆′s ₂ =c ₂ ′⊕y ₁ ′⊕y ₂ ′⊕y ₃ ′⊕y ₇ ′⊕y ₈ ′⊕y ₉′s ₃ =c ₃ ′⊕y ₁ ′⊕y ₄ ′⊕y ₅ ′⊕y ₇ ′⊕y ₈ ′⊕y ₁₀′s ₄ =c ₄ ′⊕y ₂ ′⊕y ₄ ′⊕y ₆ ′⊕y ₇ ′⊕y ₉ ′⊕y ₁₀′s ₅ =c ₅ ′⊕y ₃ ′⊕y ₅ ′⊕y ₆ ′⊕y ₈ ′⊕y ₉ ′⊕y ₁₀′

Here, [y₁′, . . . , y₁₀′, c₁′, . . . , c₅′]^(T) is the transposed columnvector of the row vector [y₁′, . . . , y₁₀′, c₁′, . . . , c₅′], and [s₁,. . . , s₅]^(T) is the transposed column vector of the row vector [s₁, .. . , s₅] of the components of the syndrome.

The implementation of the syndrome generator 61 a, which realizes theindicated equations for the components of the error syndrome s₁, s₂, s₃,s₄, s₅, for example by using XOR gates, or by using a commercialsynthesis tool, is no difficulty for a person skilled in the art.

From the error syndrome s, the decoder 62 a determines the associatedcorrection vector e=e₁, . . . , e₁₀ for the auxiliary read values y₁′, .. . , y₁₀′, which are the information bits of the considered linearerror-correcting code C. Table 15 represents the table of values of thedecoder 52.

TABLE 15 s₁ s₂ s₃ s₄ s₅ e₁ e₂ e₃ e₄ e₅ e₆ e₇ e₈ e₉ e₁₀ 0 0 0 0 0 0 0 0 00 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 01 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 00 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 10 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 11 1 0 0 0 0 0 0 0 0 0 1

All in all there are 32=2⁵ different syndrome values. Correspondingcorrection values are associated to 11 syndrome values of those in table15.

For all syndrome values not listed in table 15, the values for e₁, . . ., e₁₀ may be random, which may serve for optimizing the decoder. Forexample, all of those values may be determined to be 0. If the errorsyndrome is equal to 0, then no correction takes place, as isillustrated in the first line of table 15, as then e=0, . . . , 0. If itapplies to the error syndrome that s=h_(i), (iε{1, . . . , 10}), thenthe i-th component of the auxiliary read values is corrected, whichcorresponds to the correction of a 1-bit error. In this case, for thei-th component, e_(i)=1 applies. All other components of e are 0. Ifs=[1, 1, 0, 0]^(T)=h₃, then e=[0, 0, 1, 0, 0, 0, 0, 0, 0, 0]^(T) and thethird component of the auxiliary read values is corrected.

One possible decoder circuit is illustrated in FIG. 11.

The decoder circuit of FIG. 11 has 5 binary inputs which carry thecomponents s₁, s₂, s₃, s₄, s₅, and 10 binary outputs which output thecomponents e₁, . . . , e₁₀. It comprises 10 AND gates 110 i, i=1, . . ., 10, each having three inputs, wherein the output of the AND gate 110 icarries the value e_(i).

The input of the decoder carrying the component s₁ is connected each toa first input of the AND gates 1101, 1102, 1103, 1104, 1105 and 1106.The input of the decoder carrying the component s₂ is connected to asecond input of the AND gates 1101, 1102, 1103 and to a first input ofthe AND gates 1107, 1108 1109, each. The input of the decoder carryingthe component s₃ is connected to a first input of the AND gate 11010,each to a second input of the AND gates 1104, 1105, 1107, 1108 and tothe third input of the AND gate 1101. The input of the decoder carryingthe component s₄ is connected to a second input of the AND gates 1106,1109, 1010 and to the third input of the AND gates 1102, 1104, 1107,each. The input of the decoder carrying the component s₅ is eachconnected to the third input of the AND gates 1103, 1105, 1106, 1108,1109, 11010.

FIG. 12 shows a possible error detection circuit for the describedembodiment. It comprises a syndrome generator 1203 as it was also usedfor the corrector 17 a in FIG. 6 a, a 5 input XOR tree 1201 and a 5input OR tree 1202. The syndrome generator has 10 first binary inputs atwhich the possibly erroneous auxiliary read values y₁′, . . . , y₁₀′ areapplied and 5 further inputs which carry the possibly erroneous checkbits c₁′, . . . , c₃′ and 5 outputs at which the syndrome bits s₁, s₂,s₃, s₄, s₅ were output. The 5 outputs of the syndrome generator areconnected both to 5 inputs of the XOR tree 1201, which outputs theparity P(s) of the syndrome components P(s)=s₁⊕s₂⊕ . . . ⊕s₅ at itsoutput, and are also connected to the 5 inputs of the OR tree 1202,which outputs the OR operation OR(s)=s₁v s₂v . . . v s₅ of the syndromecomponents.

If only 1-bit errors and 2-bit errors are differentiated, as all columnsh_(i) of the H matrix H comprise odd numbers of 1s, the followingapplies:

A 1-bit error exists, when P(s)=1 and OR(s)=1.

A 2-bit error exists, when P(s)=0 and OR(s)=1.

FIG. 13 shows a joint realization of the correction circuit and theerror detection circuit. As the syndrome generator 1301 may be used bothfor error correction and also for error detection, it is possible toimplement only one syndrome generator, and to connect its outputs, whichcarry the components s₁, . . . , s₅, simultaneously to the correspondinginputs of the decoder 1304, to the inputs of the XOR tree 1302 and tothe inputs of the OR tree 1203, so that the corrector Cor 17 and thecircuit for error detection Det 120 are realized together, here.

The functioning of the considered embodiment is now to be explained.

In a memory with a subcircuit BT according to FIG. 3 c the binary valuesx₁, . . . , x₈=0, 0, 1, 1, 0, 1, 1, 1 are to be stored. The subcircuitBT in turn, as illustrated in FIG. 3 c, comprises the subcircuits BT₁38, BT₂ 39, BT₃ 310 and BT₄ 311, wherein both subcircuits BT₁ and BT₂realize the same function f as illustrated in table 6.

The subcircuit BT₁ transforms the bits x₁, x₂, x₃=001 according to table6 into the ternary states 2_(ter), 1_(ter). The subcircuit BT₂transforms the bits x₄, x₅, x₆=101 of table 6 into the ternary states0_(ter), 2_(ter). The subcircuit BT₃ maps the bit x₇=1 into the ternarystate 1_(ter), just like the subcircuit BT₄ maps the bit x₈=1 into theternary state 1_(ter). The ternary states 2_(ter), 1_(ter), 0_(ter),2_(ter), 1_(ter), 1_(ter) are written into the first 6 memory cells ofthe memory Sp 13.

The encoder Cod 12 transforms the 8 binary input values x₁, . . . ,x₈=0, 0, 1, 1, 0, 1, 1, 1 into the five binary check bits c₁, . . . ,c₅.

The functioning of the encoder may, as described, be understood so thatit first of all functionally transforms its input values into thecorresponding auxiliary read values, and generates the correspondingcheck bits from the auxiliary read values using here a linear code C,although these two steps do not have to be executed separately, forexample due to the common optimization of the corresponding subcircuits.

According to table 9, the bits x₁, x₂, x₃=0, 0, 1 are first of alltransformed into the auxiliary read values y₁, y₂, y₃, y₄=1, 1, 0, 1,the bits x₄, x₅, x₆=101 are transformed into the auxiliary read valuesy₅, y₆, y₇, y₈=0, 0, 1, 1 and bit x₇=1 is transformed into y₉=1 and bitx₈=1 is transformed into y₁₀=1 by the encoder. From the resultingauxiliary read values 1101001111, the binary check bits c₁, . . . , c₅are determined byc ₁ ,c ₂ ,c ₃ ,c ₄ ,c ₅=(1,1,0,1,0,0,1,1,1,1)·P=1,1,1,1,1as it may be directly calculated. The binary check bits c₁, c₂, c₃, c₄,c₅=1, 1, 1, 1, 1 are transformed by the subcircuits bt₁ 1010, . . . ,bt₅ 1011 into the ternary states 1_(ter), 1_(ter), 1_(ter), 1_(ter),1_(ter), and are each written into a separate one of five further cellsof the memory Sp 1013, so that all in all, the values z₁, . . . , z₄,z₅, z₆, c₁, . . . , c₅=2_(ter), 1_(ter), 0_(ter), 2_(ter), 1_(ter),1_(ter), 1_(ter), 1_(ter), 1_(ter), 1_(ter), 1_(ter) are written intothe ternary memory.

If no error occurs, then the state values z₁′, . . . , z₄′, z₅′, z₆′,c₁′, . . . , c₅′=2_(ter), 1_(ter), 0_(ter), 2_(ter), 1_(ter), 1_(ter),1_(ter), 1_(ter), 1_(ter), 1_(ter), 1_(ter) are read out. The ternaryvalues z₁′, . . . , z₆′=2_(ter), 1_(ter), 0_(ter), 2_(ter), 1_(ter),1_(ter) are transformed by the subcircuit LH 16, which is illustrated indetail in FIG. 4, into the auxiliary read values y₁′y₂′=LH¹(2_(ter))=11,y₃′, y₄′=LH²(1_(ter))=01, y₅′y₆′=LH³(0_(ter))=00, y₇′,y₈′=LH⁴(2_(ter))=11, y₉′=LH⁵(1_(ter))=1, y₁₀′=LH⁶(1_(ter))=1, usingtable 8 for LH¹, LH², LH³ and LH⁴. The ternary states 1_(ter), . . . ,1_(ter), which correspond to the check bits c₁, . . . , c₅, aretransformed by the corresponding subcircuit tb₁ 151, . . . , tb₅ 155into binary values 1_(bin), . . . , 1_(bin), so that the auxiliary readvalues y′=(1, 1, 0, 1, 0, 0, 1, 1, 1, 1) are output by the subcircuit LH16. These auxiliary read values and the check bits c₁′, . . . , c₅′=1,1, 1, 1, 1 read out from the memory are applied to the correspondinginputs of the corrector 17. In its syndrome generator 61 a of FIG. 6 a,the corrector forms the error syndrome(s ₁ , . . . ,s ₅)^(T)=H·(1,1,0,1,0,0,1,1,1,1,1,1,1,1,1)^(T)=(0,0,0,0,0)^(T),which is again simply calculated, and the decoder 62 a according totable 15, first line, outputs the correction vector e=e₁, . . . , e₁₀=0,0, whose components are combined in the XOR circuit 18 a with theauxiliary read values y′ to the corrected auxiliary read valuesy ^(c) =y ₁ ^(c) , . . . ,y ₁₀ ^(c) =y ₁′⊕0, . . . ,y₁₀′⊕0=1,1,0,1,0,0,1,1,1,1=y′⊕e.

From the corrected auxiliary read values y^(c), the subcircuit BB 19forms the corrected output values x^(c). The subcircuit BB 19 is set asillustrated in FIG. 7 c. The subcircuit BB1 78 transforms the correctedauxiliary read values y₁ ^(c), . . . , y₄ ^(c)=1, 1, 0, 1 according toTable 10 into the corrected output values x₁ ^(c),x₂ ^(c),x₃ ^(c)=0,0, 1. The subcircuit BB₂ 79 transforms the corrected auxiliary readvalues y₅ ^(c), . . . , y₈ ^(c)=0, 0, 1, 1 according to Table 10 intothe corrected output values x₄ ^(c),x₅ ^(c),x₆ ^(c)=1, 0, 1. Thesubcircuit BB₃ 710 transforms the corrected auxiliary read values y₉^(c)=1 into the corrected output value x₇=1. The subcircuit BB₄ 711transforms the corrected auxiliary read value y₁₀ ^(c)=1 into thecorrected output value x₈=1. At the circuit output thus the correctedresult x₁ ^(c), . . . , x₈ ^(c)=0, 0, 1, 1, 0, 1, 1, 1 is output.

It is now assumed that the ternary state z₁=2 written into the memory iscorrupted erroneously into the state z₁′=1 when reading out. Then whenreading out of the memory, the state values z₁′, . . . , z₄′, z₅′, z₆′,c₁′, . . . , c₅′=1_(ter), 1_(ter), 0_(ter), 2_(ter), 1_(ter), 1_(ter),1_(ter), 1_(ter), 1_(ter), 1_(ter), 1_(ter), are read out. The ternaryvalues z₁′, . . . , z₆′,=1_(ter), 1_(ter), 0_(ter), 2_(ter), 1_(ter),1_(ter) are transformed by the subcircuit LH 16, illustrated in detailin FIG. 4, using table 8, into the auxiliary read values y₁′y₂′=LH¹(1_(ter))=01, y₃′ y₄′=LH²(1_(ter))=01, y₅′ y₆′=LH³(0_(ter))=00,y₇′ y₈′=LH⁴(2_(ter))=11, y₉′=LH⁵(1_(ter))=1, y₁₀′=LH⁶(1_(ter))=1, sothat the auxiliary read values y′=(0, 1, 0, 1, 0, 0, 1, 1, 1, 1) areoutput by the subcircuit LH 16. These auxiliary read values and thecheck bits c₁′, . . . , c₅′=1, 1, 1, 1, 1 read out from the memory areapplied to the corresponding inputs of the corrector 17. In its syndromegenerator 61 a of FIG. 6, the corrector forms the error syndrome(s ₁ , . . . ,s ₅)^(T)=H·(0,1,0,1,0,0,1,1,1,1,1,1,1,1,1)^(T)=(1,1,1,0,0)^(T),and the decoder 620, according to Table 15, second line, outputs thecorrection vector e=e₁, . . . , e₁₀=1, 0, . . . , 0, which is combinedin the XOR circuit 18 a with the auxiliary read values y′ into thecorrected auxiliary read valuesy ^(c) =y ₁ ^(c) , . . . ,y ₁₀ ^(c) =y ₁′⊕1,y ₂′⊕0, . . . ,y₁₀′⊕0=1,1,0,1,0,0,1,1,1,1=y′⊕e.

Likewise, it may be gathered from FIG. 11 that for the syndrome 1, 1, 1,0, 0=s₁, s₂, s₃, s₄, s₅, the AND gate 1101 outputs the value e₁=1 at itsoutput, while for all other AND gates 110 i, i=2, . . . , 10, e_(i)=0applies. The error that the stored ternary value 2_(ter) was erroneouslycorrupted into 1_(ter) has been corrected in the auxiliary read values.From the corrected auxiliary read values y^(c), the subcircuit BB 19, asdescribed, forms the corrected output values x^(c).

At the circuit output, thus, again the corrected result x₁ ^(c), . . . ,x₈ ^(c)=0, 0, 1, 1, 0, 1, 1, 1 is output.

If an error detection circuit Det 120 exists, which as in FIG. 12comprises the syndrome generator 51, the XOR tree 1201 and the OR tree1202, then it applies for the error syndrome s₁, . . . , s₅=1, 1, 1, 0,0 that for the parity P(s) of the component of error syndrome P(s)=1applies and for the OR operation OR(s)=1 applies, so that a 1-bit erroris indicated.

Embodiments provide circuitry configured to store and to error correctsequences x₁, . . . , x_(n) of binary data with n≧3, which may be storedin a memory comprising memory cells which may take on ternary states,wherein from the sequences of binary states certain ternary values arestored in memory cells which may take on ternary states, and whereinwhen reading from the memory of possibly erroneous ternary values fromthe memory cells, which may take on ternary states, binary auxiliaryread values are formed, wherein an encoder exists which outputs binarycheck bits at its outputs depending on the data x₁, . . . , x_(n) beinginput at its at least n binary inputs, wherein outputs of the encoder,which carry a binary check bit, are connected to a data input of amemory cell of the memory when writing into the memory, wherein a datainput of a memory cell connected to an output of the encoder is notconnected to any further output of the encoder, and wherein the encoderis configured, so that the binary check bits determined by the encoderand the binary auxiliary read values in the error-free case, form acodeword of an error-correcting code.

According to some embodiments, the encoder is implemented so that theencoder comprises, apart from n binary inputs for the input of the datavalues x₁, . . . , x_(n) furthermore q binary inputs for the input ofbinary values A=A₁, . . . , A_(q)=F (a₁, . . . , a_(Q)) determined fromthe address bits (a=a₁, . . . , a_(Q)), wherein F is a unique mapping ofQ-digit binary values into q-digit binary values, wherein Q is the wordwidth of the memory address and wherein 1≦q≦Q applies, and wherein theencoder is configured, so that the binary check bits determined by theencoder, the values A₁ . . . , Aq determined from the address bits andthe binary auxiliary read values form in the error-free case a codewordof an error-correcting code.

Some embodiments provide circuitry for storing of sequences of binaryvalues x₁, . . . , x_(n) in a memory, wherein n≧3, wherein memory cellsof a non-empty subset of memory cells of the memory may take on threestate values, and wherein all memory cells which may not take on threestates values may take on two state values, with the following features:

1. A subcircuit BT with n binary inputs and M outputs for thetransformation of n binary input values x₁, . . . , x_(n) into M outputvaluesz ₁ , . . . ,z _(m) ,z _(m+1) , . . . ,z _(M) =BT(x ₁ , . . . ,x _(n))exists, wherein 2≦m≦M and wherein M<n and wherein n≧4,wherein the output values z₁, . . . , z_(m) may take on three differentvalues depending on the input values, and wherein the output valuesz_(m+1), . . . , z_(M) may take on at most two different valuesdepending on the input values,2. The M outputs of the subcircuit BT are fed into M data inputs of amemory Sp, wherein, when writing into the memory, the output values z₁,. . . , z_(m) of the subcircuit BT are stored into memory cells, whichmay take on 3 states, and wherein the output values z_(m+1), . . . ,z_(M) are stored in memory cells which may take on at least two states,3. A subcircuit LH exists for determining binary auxiliary read valuesy ₁ ′, . . . ,y _(k) ′=LH(z ₁ ′, . . . ,z _(m) ′,z _(m+1) ′, . . . ,z_(M)′)with M inputs and k outputs, wherein, when reading from the memory, mfirst inputs of the subcircuit LH are connected to the data outputs ofthe memory cells of memory Sp, into which, when writing the ternaryvalues z₁, . . . , z_(m) are written, and from which, when reading, thepossibly erroneous ternary values z₁′, . . . , z_(m)′ are read out, andthe further M−m inputs of the subcircuit LH are connected to the dataoutputs of the memory cells into which, when writing, the valuesz_(m+1), . . . , z_(M) are written, and from which, when reading, thepossible erroneous values z_(m+1)′, . . . , z_(M)′ are read out, andwhich outputs k binary auxiliary read values y₁′, . . . , y_(k)′ withk≧m+M at its k outputs.4. An encoder Cod with n binary inputs and l binary outputs exist fordetermining l binary check bits c₁, . . . , c_(l) from the n binaryinput values x₁, . . . , x_(n) withc ₁ , . . . ,c _(l)=Cod(x ₁ , . . . ,x _(n))wherein at n binary inputs of the encoder Cod, the binary input valuesx₁, . . . , x_(n) are applied, and at l binary outputs, correspondingbinary check bits c₁, . . . , c_(l) are output, and wherein the encoderis configured, so that it determines the check bits c₁, . . . c_(l) fromthe input values x₁, . . . , x_(n) so that the bitsy ₁ , . . . ,y _(k) ,c ₁ , . . . ,c _(l)form a codeword of an error-correcting code C of the length k+l with kdata bits and l check bits and the bitsy ₁ , . . . ,y _(k) =LH[BT(x ₁ , . . . ,x _(n))]are functionally determined by the subsequent transformations of thedata bits x₁, . . . , x_(n) by the subcircuit BT and LH,5. For j=1, . . . , l, the output of the encoder Cod carrying the checkbit c_(j) is connected to the data input of a j-th memory cell whenwriting into the memory, wherein the data input of this j-th memory cellis connected to no further output of the encoder,6. A corrector Cor for an error-correcting code C with l first binaryinputs and k second binary inputs exist, wherein for j=1, . . . , l, thej-th input of the l first inputs of the corrector is connected to thedata output of the memory cell, which is connected to the j-th output ofthe encoder when writing so that when an error occurred at its j-thinput, the value c_(j)′ of the possibly erroneous j-th check bit isapplied, and when no error occurred the correct value c_(j) of the j-thcheck bit is applied, and wherein at the k bits wide second input of thecorrector, the possibly erroneous auxiliary read values y₁′, . . . ,y_(k)′ output by the subcircuit LH are applied and the corrector isconfigured so that it outputs a correction vector e=e₁, . . . , e_(k) atits k bit wide output so thaty ₁ , . . . ,y _(k) =[y ₁ ′op ₁ e ₁ ], . . . ,[y _(k) ′op _(k) e _(k)]applies, when an error which may be corrected by the error-correctingcode C occurs and op₁, . . . , op_(k) are uniquely invertible binaryoperations, and where the correction vector e is equal to the zerovector e⁰=e₁ ⁰, . . . , e_(k) ⁰, when no error occurred, where e_(i) ⁰is for i=1, . . . , k the zero element of the operation op_(i).7. A combinational circuit Vkn with a k bit wide first input and a k bitwide second input and a k bit wide output exist, wherein the first k bitwide input is connected to the k bit wide output of the subcircuit LHwhich carries the possibly erroneous auxiliary read values y₁′, . . . ,y_(k)′, and the second k bit wide input is connected to the k bit wideoutput of the corrector Cor which carries the correction vector e=e₁, .. . , e_(k), wherein the combinational circuit is configured so that itoutputs at its k output the corrected auxiliary read valuey ₁ ^(cor) , . . . ,y _(k) ^(cor) =[y ₁ ′op ₁ e ₁ ], . . . ,[y _(k) ′op_(k) e _(k)]wherein op₁, . . . , op_(k) are uniquely invertible operations and y₁^(cor), . . . , y_(k) ^(cor)=y₁, . . . , y_(k) applies when no error oran error correctable by the code C occurred,8. A subcircuit BB for the transformation of the binary correctedauxiliary read values y₁ ^(cor), . . . , y_(k) ^(cor) into n binarycorrected data bits x₁ ^(cor), . . . , x_(n) ^(cor)=BB[y₁ ^(cor), . . ., y_(k) ^(cor)] exist which is configured so that when y₁ ^(cor), . . ., y_(k) ^(cor)=y₁, . . . , y_(k) applies, also x₁, . . . , x_(n)=x₁^(cor), . . . , x_(n) ^(cor) applies,9. The subcircuit BT 11, LH 16 and BB 19 are configured so that theinput values x=x₁, . . . , x_(n) are reproduced at least when no erroroccurred after the subsequent transformations of the input values by thesubcircuit BT, LH and BB andBB{LH[BT(x ₁ , . . . ,x _(n))]}=x ₁ , . . . ,x _(n)applies.

In some embodiments, the encoder is implemented so that check bitsdetermined by the encoder additionally depend on values of address bitsof the write address a=a₁, . . . , a_(Q), and the corrector isimplemented so that the correcting vector determined by the correctoradditionally depends on corresponding values of address bits of the readaddress a′=a₁′, . . . , a_(Q)′.

According to embodiments, the encoder comprises in addition to n binaryinputs for the inputs of the data bits x₁, . . . x_(n) further q, q≧1binary inputs for the input of q bits A₁, . . . , A_(q) derived from theaddress bits of the read address a=a₁, . . . , a_(Q)A ₁ , . . . ,A _(q) =F(a ₁ , . . . ,a _(Q))wherein F is a unique assignment of the bits A₁, . . . , A_(q) to thebits a₁, . . . , a_(Q) of the read address, and wherein the encoder isconfigured so that c₁, . . . , c_(l), y₁, . . . , y_(k), A₁, . . . ,A_(q) is a codeword of an error-correcting code C and wherein thecorrector, apart from the l binary inputs for the input of the possiblyerroneous check bits c₁′ . . . c_(l)′ and the k possibly erroneousauxiliary read values y₁′, . . . , y_(k)′ comprises further q binaryinputs for the input of q bits A₁′, . . . , A_(q)′ derived from the Qaddress bits of the read address a′=a₁′, . . . , a_(Q)′,A ₁ ′, . . . ,A _(q) ′=F(a ₁ ′, . . . ,a _(Q)′).

In some embodiments, the corrector, apart from k binary outputs for theoutput of the correction values e₁, . . . , e_(k) for the correction ofthe auxiliary read values y₁′, . . . , y_(k)′ comprises further q binaryoutputs for the output of correction values e₁ ^(A), . . . , e_(q) ^(A)for the correction of the bits A₁′, . . . , A_(q)′ derived from theaddress bits of the read address.

According to embodiments, q=1 applies andA ₁ =F(a ₁ , . . . ,a _(Q))=a ₁ ⊕ . . . ⊕a _(Q)is the parity of the write address andA ₁ ′=F(a ₁ ′, . . . ,a _(Q)′)=a ₁ ′⊕ . . . ⊕a _(Q)′is the parity of the read address.

In embodiments, q=Q, A₁, . . . , A_(Q)=a₁, . . . , a_(q) and A₁′, . . ., A_(Q)′=a₁′, . . . , a_(q)′ applies.

According to some embodiments, the outputs of the corrector carrying thecorrection values e₁ ^(A), . . . , e_(q) ^(A) are fed into q inputs ofan error detection circuit which, when the correction value e₁ ^(A), . .. , e_(q) ^(A) correspond to an address correction indicates an addresserror at its output.

In embodiments, the error detection circuit is realised as a NOR circuitwith q inputs in which the q inputs are connected to the q correctionvalues e₁ ^(A), . . . , e_(q) ^(A) of the outputs of the corrector.

According to some embodiments, the code C is a linear code.

In embodiments, the corrector is a series circuit of a syndromegenerator and a decoder.

According to embodiments, the corrector is a series connection of asyndrome generator and a decoder and the syndrome generator is connectedto an address error determiner which outputs a signal “address error”when the error syndrome determined by the syndrome generator correspondsto an address error.

In some embodiments, for j=1, . . . , l the j-th output for the checkbit c_(j) of the encoder, the check bit c_(j) is connected to the inputof a subcircuit bt_(j) for the transformation of a binary value c_(j)into a ternary value c_(j) ^(ter) in which the output when writing isconnected to the data input of a memory cell for storing the ternaryvalue c_(j) ^(ter), and wherein when reading the data output of theternary memory cell for storing the ternary value c_(j) ^(ter) isconnected to the input of a subcircuit tb_(j) for the transformation ofa ternary value c_(j) ^(ter′) into a binary value c_(j)′, in which theoutput is connected to the corresponding inputs of the corrector,wherein tb_(j)[bt_(j)(c_(j))]=c_(j) applies.

According to embodiments, the binary value 0 is transformed into aminimum ternary value by the subcircuit bt_(j), and wherein the value 1is transformed into a maximum ternary value by the subcircuit bt_(j).

In embodiments, the binary value 0 is transformed into a maximum ternaryvalue by the subcircuit bt_(j), and wherein the value 1 is transformedinto a minimum ternary value by the subcircuit bt_(j).

According to embodiments, for at least one jε{1, . . . , l}, the j-thoutput of the coder, when writing, is connected directly to the datainput of a memory cell for storing a binary value c_(j), and wherein,when reading, the data output of the memory cell for storing the binaryvalue c_(j) is directly connected to the corresponding input of thecorrector.

In some embodiments, the code C is a linear code with a generator matrixG=(l, P) and the coder is implemented so that the check bits c=c₁, . . ., c_(l) are determined according to the relationc=c ₁ , . . . ,c _(l)=′(LH[BT(x ₁ , . . . ,x _(n))])·P=(y ₁ , . . . ,y_(k))·Pwherein G is a (k, k+l) matrix when the address bits are not included inerror detection and the check bits are determined according to therelationc=c ₁ , . . . ,c _(l) ={LH[BT(x ₁ , . . . ,x _(n))],A ₁ , . . . ,A _(q)}·P=(y ₁ , . . . ,y _(k) ,A ₁ , . . . ,A _(q))·P,wherein G is a (k+q, k+l+q) matrix when the address bits are included inerror detection via the bits A₁, . . . , A_(q) derived from the addressbits a₁, . . . , a_(Q).

According to embodiments, the subcircuit BT 11 for the transformation ofthe input values x₁, . . . , x_(n) into the output values z₁, . . . ,z_(m), z_(m+1), . . . , z_(M) is a series connection of a subcircuit BSS94 for the transformation of the input values x₁, . . . , x_(n) into kbinary auxiliary write values y₁ ^(s), . . . , y_(k) ^(s) and asubcircuit BTS 95 for the transformation of the binary auxiliary writevalues y₁ ^(s), . . . , y_(k) ^(s) into the output values z₁, . . . ,z_(m), z_(m+1), . . . , z_(M) of the circuit BT 11.

In embodiments, the subcircuit BSS is implemented so that the auxiliarywrite values y₁ ^(s), . . . , y_(k) ^(s) determined by the subcircuitBSS are equal to the error-free auxiliary read values y₁, . . . , y_(k)determined by the subcircuits BB and LH, and the encoder is implementedso that it determines the check bits c₁, . . . , c_(l) using theauxiliary write values output by the subcircuit BBS.

According to embodiments, the encoder is implemented so that the checkbits c=c₁, . . . , c_(l) are determined according to the relationc=c ₁ , . . . ,c _(l) =BBS(x ₁ , . . . ,x _(n))·P=(y ₁ ^(s) , . . . ,y_(k) ^(s))·Pwherein G is a (k, k+l) matrix when the address bits are not included inerror detection and are determined according to the relationc=c ₁ , . . . ,c _(l) ={BBS(x ₁ , . . . ,x _(n)),A ₁ , . . . ,A _(q)}·P=(y ₁ ^(s) , . . . ,y _(k) ^(s) ,A ₁ , . . . ,A _(q))·P,wherein G is a (k+q, k+l+q) matrix when the address bits are included inerror detection via the bits A₁, . . . , A_(q) derived from the addressbits a₁, . . . , a_(Q).

According to an embodiment, the subcircuit LH 16 for determining binaryauxiliary read values y₁′, . . . , y_(k)′=LH(z₁′, . . . , z_(M)′) fromthe state values z₁′, . . . , z_(M)′ read out from the memory isimplemented so that component-wise to each ternary state componenty_(i)′, i=1, . . . , m at least two binary auxiliary read values areassigned and to each binary state component z_(m+1), . . . , z_(M) atleast one binary auxiliary read value is assigned, and so that k≧m+Mapplies,

Although some aspects have been described in the context of anapparatus, it is clear that these aspects also represent a descriptionof the corresponding method, where a block or device corresponds to amethod step or a feature of a method step. Analogously, aspectsdescribed in the context of a method step also represent a descriptionof a corresponding unit or item or feature of a corresponding apparatus.

The inventive decomposed signal can be stored on a digital storagemedium or can be transmitted on a transmission medium such as a wirelesstransmission medium or a wired transmission medium such as the Internet.

Depending on certain implementation requirements, embodiments ofembodiments can be implemented in hardware or in software. Theimplementation can be performed using a digital storage medium, forexample a floppy disk, a DVD, a CD, a ROM, a PROM, an EPROM, an EEPROMor a FLASH memory, having electronically readable control signals storedthereon, which cooperate (or are capable of cooperating) with aprogrammable computer system such that the respective method isperformed.

Some embodiments according to embodiments comprise a non-transitory datacarrier having electronically readable control signals, which arecapable of cooperating with a programmable computer system, such thatone of the methods described herein is performed.

Generally, embodiments of the present invention can be implemented as acomputer program product with a program code, the program code beingoperative for performing one of the methods when the computer programproduct runs on a computer. The program code may for example be storedon a machine readable carrier.

Other embodiments comprise the computer program for performing one ofthe methods described herein, stored on a machine readable carrier.

In other words, an embodiment of the inventive method is, therefore, acomputer program having a program code for performing one of the methodsdescribed herein, when the computer program runs on a computer.

A further embodiment of the inventive methods is, therefore, a datacarrier (or a digital storage medium, or a computer-readable medium)comprising, recorded thereon, the computer program for performing one ofthe methods described herein.

A further embodiment of the inventive method is, therefore, a datastream or a sequence of signals representing the computer program forperforming one of the methods described herein. The data stream or thesequence of signals may for example be configured to be transferred viaa data communication connection, for example via the Internet.

A further embodiment comprises a processing means, for example acomputer, or a programmable logic device, configured to or adapted toperform one of the methods described herein.

A further embodiment comprises a computer having installed thereon thecomputer program for performing one of the methods described herein.

In some embodiments, a programmable logic device (for example a fieldprogrammable gate array) may be used to perform some or all of thefunctionalities of the methods described herein. In some embodiments, afield programmable gate array may cooperate with a microprocessor inorder to perform one of the methods described herein. Generally, themethods are performed by any hardware apparatus.

While this invention has been described in terms of several advantageousembodiments, there are alterations, permutations, and equivalents whichfall within the scope of this invention. It should also be noted thatthere are many alternative ways of implementing the methods andcompositions of the present invention. It is therefore intended that thefollowing appended claims be interpreted as including all suchalterations, permutations, and equivalents as fall within the truespirit and scope of the present invention.

The above described embodiments are merely illustrative for theprinciples of the present invention. It is understood that modificationsand variations of the arrangements and the details described herein willbe apparent to others skilled in the art. It is the intent, therefore,to be limited only by the scope of the impending patent claims and notby the specific details presented by way of description and explanationof the embodiments herein.

Although each claim only refers back to one single claim, the disclosurealso covers any conceivable combination of claims.

The invention claimed is:
 1. A circuitry, comprising: a memorycomprising a plurality of memory cells, wherein one or more of theplurality of memory cells of the memory are each configured to take onone of at least three different states; a first subcircuit configured togenerate a plurality of output values based on a sequence of binaryvalues, wherein each of the plurality of output values is equal to oneof at least three different basic values, wherein the first subcircuitis configured to store each of the output values as a state value in adifferent one of the one or more memory cells which are each configuredto take on one of the at least three different states; a secondsubcircuit configured to read the state value from each of at least oneof the memory cells which are configured to take on one of the at leastthree different states, wherein the state value is one the threedifferent basic values, wherein the second subcircuit is furthermoreconfigured to determine binary auxiliary read values based on the statevalue of each of the at least one of the memory cells, and an encoderconfigured to generate one or more binary check bits based on at least aportion of the sequence of binary values, wherein an error-correctingcode comprises a plurality of codewords, and wherein the encoder isconfigured to generate the one or more binary check bits so that thebinary auxiliary read values and the one or more binary check bitstogether form one of the codewords of the error-correcting code, whenthe binary auxiliary read values and the one or more binary check bitsare error-free, wherein the encoder is configured to store each of thegenerated one or more check bits in one or more of the memory cells ofthe memory, such that each of the one or more check bits is stored in adifferent one of the memory cells of the memory, wherein each one of thememory cells in which a check bit is stored is configured to take on oneof at least two different states.
 2. The circuitry according to claim 1,wherein the one or more of the plurality of memory cells of the memory,which are each configured to take on one of at least three differentstates, are ternary memory cells, wherein the ternary memory cells areconfigured to take on one of exactly three different states, wherein thefirst subcircuit is configured to generate the plurality of outputvalues such that each of the plurality of output values has one ofexactly three different basic values, wherein the first subcircuit isconfigured to store each of the output values as a state value in adifferent one of the ternary memory cells, and wherein the secondsubcircuit is configured to read the one or more state values from atleast one of the ternary memory cells, wherein each of the one or morestate values has one of exactly three different basic values, whereinthe second subcircuit is furthermore configured to determine the binaryauxiliary read values based on the one or more state values.
 3. Thecircuitry according to claim 1, wherein the circuitry furthermorecomprises a corrector and a combinational circuit, wherein the secondsubcircuit is configured to feed the binary auxiliary read values intothe corrector and into the combinational circuit, wherein the correctoris configured to read the one or more check bits from one or more of thememory cells of the memory, and generate the error correction bits basedon the binary auxiliary read values and the one or more check bits, andfeed the error correction bits into the combinational circuit, andwherein the combinational circuit is configured to conduct errorcorrection on the binary auxiliary read values based on the errorcorrection bits to obtain binary auxiliary error-free read values, ifthe error is correctable by the error-correcting code.
 4. The circuitryaccording to claim 3, wherein the combinational circuit is configured toconduct error correction such that the binary auxiliary error-free readvalues and the one or more check bits form one of the codewords of theerror-correcting code.
 5. The circuitry according to claim 3, whereinthe circuitry further comprises a third subcircuit configured totransform the binary auxiliary error-free read values into n binaryerror-corrected data bits, wherein n is an integer.
 6. The circuitryaccording to claim 2, wherein the sequence of binary values comprises nbits, wherein n is an integer, and n≧3, wherein the encoder comprises atleast n encoder input ports configured to receive the binary data,wherein the encoder comprises one or more encoder output ports, whereinthe encoder is configured to receive the sequence of binary values atthe at least n encoder input ports, wherein the encoder is configured tooutput the one or more binary check bits at the one or more encoderoutput ports, wherein one or more of the encoder output ports, which areconfigured to carry one or more of the binary check bits, respectively,are connected to an input port of one of the memory cells of the memory,respectively, when writing into the memory, wherein each input port ofeach of the memory cells which is connected to one of the output portsof the encoder is not connected to any further output port of theencoder, and wherein the encoder is configured so that the one or morebinary check bits and the binary auxiliary read values determined by theencoder in the error-free case form one of the codewords of theerror-correcting code.
 7. The circuitry according to claim 1, whereinthe encoder is configured to generate the one or more binary check bitsbased on address bits a=a₁, . . . , a_(Q).
 8. The circuitry according toclaim 7, wherein the encoder is configured to generate the one or morebinary check bits such that the binary check bits determined by theencoder, binary values A₁ . . . , Aq depending on the address bits a=a₁,. . . , a_(Q) and the binary auxiliary read values form in theerror-free case a codeword of an error-correcting code.
 9. The circuitryaccording to claim 6, wherein the encoder is implemented so that theencoder comprises furthermore q binary inputs for the input of binaryvalues A₁, . . . , A_(q), wherein A₁, . . . , A_(q)=F(a₁, . . . , a_(Q))applies, wherein a₁, . . . , a_(Q) are address bits, wherein F is aunique mapping of Q-digit binary values into q-digit binary values,wherein Q is the word width of a memory address of the memory, wherein1≦q≦Q applies, and wherein the encoder is configured, so that the binarycheck bits determined by the encoder, the values A₁ . . . , Aqdetermined from the address bits and the binary auxiliary read valuesform in the error-free case a codeword of an error-correcting code. 10.A circuitry, comprising: a memory comprising a plurality of memorycells, wherein one or more of the plurality of memory cells of thememory are ternary memory cells each being configured to take on one ofthree different states; a first subcircuit configured to generate aplurality of output values, based on a sequence of binary values,wherein each of the plurality of output values has one of threedifferent basic values, wherein the first subcircuit is configured tostore each of the output values as a state value in a different one ofthe one or more ternary memory cells which are each configured to takeon one of the three different states; a second subcircuit configured toread the state value from each of at least one of the ternary memorycells which are configured to take on one of the three different states,wherein the state value is one of the three different basic values,wherein the second subcircuit is furthermore configured to determinebinary auxiliary read values based on the state value of each of the atleast one of the ternary memory cells; an encoder configured to generateone or more binary check bits based on at least a portion of thesequence of binary values, wherein an error-correcting code comprises aplurality of codewords, and wherein the encoder is configured togenerate the one or more binary check bits so that the binary auxiliaryread values and the one or more binary check bits together form one ofthe codewords of the error-correcting code, when the binary auxiliaryread values and the one or more binary check bits are error-free,wherein the encoder is configured to store each of the generated one ormore check bits in one or more of the memory cells of the memory, suchthat each of the one or more check bits is stored in a different one ofthe memory cells of the memory, wherein each one of the memory cells inwhich a check bit is stored is configured to take on one of at least twodifferent states; a corrector; a combinational circuit; and a thirdsubcircuit, wherein the second subcircuit is configured to feed thebinary auxiliary read values into the corrector and into thecombinational circuit, wherein the corrector his configured to read theone or more check bits from one or more of the memory cells of thememory, wherein the corrector is configured to generate the errorcorrection bits based on the binary auxiliary read values and the one ormore check bits, and wherein the corrector is configured to feed theerror correction bits into the combinational circuit, wherein thecombinational circuit is configured to conduct error correction on thebinary auxiliary read values based on the error correction bits toobtain binary auxiliary error-free read values, and wherein the thirdsubcircuit is configured to transform the binary auxiliary error-freeread values into n binary corrected data bits.
 11. A circuitry beingconfigured to store sequences of binary values x₁, . . . , x_(n) in amemory comprising memory cells, wherein n≧4, wherein each of the memorycells of the memory is either configured to take on one of three statevalues or to take on one of two state values, wherein at least one ofthe memory cells of the memory is configured to take on one of threestate values, and wherein the circuitry comprises: a first subcircuithaving n binary inputs and M outputs, wherein the first subcircuit isconfigured to transform n binary input values x₁, . . . , x_(n) into Moutput values z₁, . . . , z_(m), z_(m+1), . . . , z_(M)=BT(x₁, . . . ,x_(n)), wherein 2≦m≦M, wherein M<n, wherein each of the output valuesz₁, . . . , z_(m) has one of three different values depending on thebinary input values, and wherein each of the output values z_(m+1), . .. , z_(M) has one of at most two different values depending on thebinary input values, wherein the first subcircuit has M outputs whichare connected with M data inputs of the memory, wherein, when writinginto the memory, the output values z₁, . . . , z_(m) of the firstsubcircuit are stored into the memory cells of the memory, which areconfigured to take on one of three states, and wherein the output valuesz_(m+1), . . . , z_(M) are stored in memory cells which are configuredto take on one of at least two state values; a second subcircuitconfigured to determine binary auxiliary read values y₁′, . . . ,y_(k)′=LH(z₁′, . . . , z_(m)′, z_(m+1)′, . . . , z_(M)′), wherein thesecond subcircuit has M inputs and k outputs, wherein, when reading fromthe memory, m first inputs of the inputs of the second subcircuit areconnected to the data outputs of the memory cells of memory, into which,when writing, the ternary values z₁, . . . , z_(m) are written, and fromwhich, when reading, ternary values z₁′, . . . , z_(m)′ are read outwhich are erroneous or not erroneous, and further M−m inputs of thesecond subcircuit are connected to the data outputs of the memory cellsinto which, when writing, the values z_(m), . . . , z_(M) are written,and from which, when reading, the values z_(m+1)′, . . . , z_(M)′ areread out which are erroneous or not erroneous, and wherein the secondsubcircuit outputs k binary auxiliary read values y₁′, . . . , y_(k)′with k≧m+M at its k outputs; an encoder with n binary inputs and Ibinary outputs configured to determine I binary check bits c₁, . . . ,c_(l) from the n binary input values x₁, . . . , x_(n) with c₁, . . . ,c_(l)=Cod(x₁, . . . , x_(n)), wherein at n binary inputs of the encoder,the binary input values x₁, . . . , x_(n) are applied, and at l binaryoutputs of the encoder, binary check bits c₁, . . . , c_(l) determinedby the binary input values x₁, . . . , x_(n) are output, and wherein theencoder is configured to determine the check bits c₁, . . . c_(l) fromthe binary input values x₁, . . . , x_(n) so that bits y₁, . . . ,y_(k), c₁, . . . , c_(l) form a codeword of an error-correcting code ofthe length k+l with k data bits and l check bits, such that each of thebinary check bits is stored in a different one of the memory cells. 12.The circuitry according to claim 11, wherein bits y₁, . . . ,y_(k)=LH[BT(x₁, . . . , x_(n))] are determined by transformations of thebinary input values x₁, . . . , x_(n) by the first subcircuit and by thesecond subcircuit, wherein, for j=1, . . . , l, the output of theencoder carrying the check bit c_(j) is connected to the data input of aj-th memory cell when writing into the memory, wherein the data input ofthis j-th memory cell is connected to no further output of the encoder.13. The circuitry according to claim 12, wherein the circuitry furthercomprises a corrector for an error-correcting code with l first binaryinputs and k second binary inputs, wherein for j=1, . . . , l, the j-thinput of the l first inputs of the corrector is connected to the dataoutput of the memory cell, which is connected to the j-th output of theencoder when writing so that when an error occurs at its j-th input, thevalue c′_(j) of the j-th check bit, which is erroneous or not erroneous,is applied, and when no error occurs the corrected value c_(j) of thej-th check bit is applied, and wherein at the k bits wide second inputof the corrector, the auxiliary read values y₁′, . . . , y_(k)′, whichare erroneous or not erroneous, output by the second subcircuit areapplied, and wherein the corrector is configured to output a correctionvector e=e₁, . . . , e_(k) at its k bit wide output so that y₁, . . . ,y_(k)=[y₁′ op₁ e₁], . . . , [y_(k)′ op_(k)e_(k)] applies, when an errorwhich may be corrected by the error-correcting code occurs and op₁, . .. , op_(k) are uniquely invertible binary operations.
 14. The circuitryaccording to claim 13, wherein the circuitry further comprises acombinational circuit with a k bit wide first input and a k bit widesecond input and a k bit wide output, wherein the first k bit wide inputof the combinational circuit is connected to the k bit wide output ofthe second subcircuit which carries the auxiliary read values y₁′, . . ., y_(k)′, which are erroneous or not erroneous, and wherein the second kbit wide input of the combinational circuit is connected to the k bitwide output of the corrector which carries the correction vector e=e₁, .. . , e_(k), and wherein the combinational circuit is configured tooutput at its k outputs the corrected auxiliary read value y₁ ^(cor), .. . , y_(k) ^(cor)=[t₁′ op₁ e₁], . . . , [y_(k)′ op_(k) e_(k)], whereinop₁, . . . , op_(k) are uniquely invertible operations, and wherein y₁^(cor), . . . , y_(k) ^(cor)=y₁, . . . , y_(k) applies when no error oran error correctable by the code exist.
 15. The circuitry according toclaim 14, wherein the circuitry further comprises a third subcircuitconfigured to transform the binary corrected auxiliary read values y₁^(cor), . . . , y_(k) ^(cor) into n binary corrected data bits x₁^(cor), . . . , x_(n) ^(cor)=BB[y₁ ^(cor), . . . , y_(k) ^(cor)],wherein the third subcircuit is configured so that when y₁ ^(cor), . . ., y_(k) ^(cor)=y₁, . . . , y_(k) applies, also x₁, . . . x_(n)=x₁^(cor), . . . , x_(n) ^(cor) applies.
 16. The circuitry according toclaim 15, wherein the first subcircuit, the second subcircuit and thethird subcircuit are configured so that the input values x=x₁, . . . ,x_(n) are reproduced at least when no error occurred after thesubsequent transformations of the input values by the first subcircuit,by the second subcircuit and by the third subcircuit, and whereinBB{LH[BT(x₁, . . . , x_(n))]}=x₁, . . . , x_(n) applies.
 17. Thecircuitry according to claim 16, wherein the encoder is configured sothat check bits determined by the encoder furthermore depend on valuesof address bits of a write address a=a₁, . . . , a_(Q), and wherein thecorrector is configured so that the correcting vector determined by thecorrector additionally depends on corresponding values of address bitsof a read address.
 18. The circuitry according to claim 17, wherein theencoder comprises, in addition to n binary inputs for the inputs of thebinary input values x₁, . . . x_(n), further q binary inputs for theinput of q bits A₁, . . . , A_(q), q≧1, derived from the address bits ofthe read address, wherein A₁, . . . , A_(q)=F(a₁, . . . , a_(Q))applies, wherein F is a unique assignment of the bits A₁, . . . , A_(q)to the bits a₁, . . . , a_(Q) of the read address, and wherein theencoder is configured so that c₁, . . . , c_(l), y₁, . . . , y_(k), A₁,. . . , A_(q) is a codeword of an error-correcting code, wherein thecorrector, apart from the l binary inputs for the input of the checkbits c₁′ . . . c_(l)′, which are erroneous or not erroneous, and the kauxiliary read values y₁′, . . . , y_(k)′, which are erroneous or noterroneous, comprises further q binary inputs for the input of q bitsA₁′, . . . , A_(q)′ derived from the Q address bits of the read address,and wherein A₁′, . . . , A_(q)′=F(a₁′, . . . , a_(Q)′) applies.
 19. Thecircuitry according to claim 18, wherein the corrector, apart from kbinary outputs for the output of the correction values e₁, . . . , e_(k)for the correction of the auxiliary read values y₁′, . . . , y_(k)′,comprises further q binary outputs for the output of correction valuese₁ ^(A), . . . , e_(q) ^(A) for the correction of the bits A₁′, . . . ,A_(q)′ derived from the address bits of the read address.
 20. Thecircuitry according to claim 18, wherein q=1 and A₁=F(a₁, . . . ,a_(Q))=a₁⊕ . . . ⊕a_(Q) is the parity of the read address and A₁′=F(a₁′,. . . , a_(Q)′)=a₁′⊕ . . . ⊕a_(Q)′ is the parity of the write address.21. The circuitry according to claim 18, wherein q=Q, A₁, . . . ,A_(Q)=a₁, . . . . , a_(q) and A₁′, . . . , A_(Q)′=a₁′, . . . , a_(q)′.22. The circuitry according to claim 19, wherein the outputs of thecorrector carrying the correction values e₁ ^(A), . . . , e_(q) ^(A) arefed into q inputs of an error detection circuit which, when thecorrection value e₁ ^(A), . . . , e_(q) ^(A) corresponds to an addresscorrection and indicates an address error at its output.
 23. Thecircuitry according to claim 22, wherein the error detection circuitcomprises a NOR circuit with q inputs in which the q inputs areconnected to the q correction values e₁ ^(A), . . . , e_(q) ^(A) of theoutputs of the corrector.
 24. The circuitry according to claim 16,wherein the code is a linear code.
 25. The circuitry according to claim16, wherein the corrector comprises a series connected circuit of asyndrome generator and a decoder.
 26. The circuitry according to claim17, wherein the corrector comprises a series connection of a syndromegenerator and a decoder, and the syndrome generator is connected to anaddress error determiner which outputs a signal “address error” when theerror syndrome determined by the syndrome generator corresponds to anaddress error.
 27. The circuitry according to claim 16, wherein for j=1,. . . , l the j-th output of the encoder, wherein the check bit c_(j) isconnected to the input of a fourth subcircuit for the transformation ofa binary value c_(j) into a ternary value c_(j) ^(ter) in which theoutput when writing is connected to the data input of a memory cell forstoring the ternary value c_(j) ^(ter), and wherein when writing thedata output of the ternary memory cell for storing the ternary valuec_(j) ^(ter) is connected to the input of a fifth subcircuit for thetransformation of a ternary value c_(j) ^(ter′) into a binary valuec′_(j), in which the output is connected to the corresponding inputs ofthe corrector, wherein tb_(j)[bt_(j)(c_(j))]=c_(j) applies.
 28. Thecircuitry according to claim 27, wherein the binary value 0 istransformed into a minimum ternary value by the fourth subcircuit, andwherein the value 1 is transformed into a maximum ternary value by thefourth subcircuit.
 29. The circuitry according to claim 27, wherein thebinary value 0 is transformed into a maximum ternary value by the fourthsubcircuit, and wherein the value 1 is transformed into a minimumternary value by the fourth subcircuit.
 30. The circuitry according toclaim 16, wherein for at least one jε{1, . . . , l}, the j-th output ofthe coder, when writing, is connected directly to a data input of amemory cell for storing a binary value c_(j), and wherein, when reading,the data output of the memory cell employed for storing the binary valuec_(j), is directly connected to the corresponding input of thecorrector.
 31. The circuitry according to claim 16, wherein the code isa linear code with a generator matrix G=(l, P) and the coder isimplemented so that the check bits c=c₁, . . . , c_(l) are determinedaccording to the relationc=c ₁ , . . . ,c _(l)=LH[BT(x ₁ , . . . ,x _(n))]·P=(y ₁ , . . . ,y_(k))·P wherein G is a (k, k+l)-matrix, l is a k-dimensional identitymatrix and P is a (k, l)-parity matrix, when the address bits are notincluded in error correction or error detection, where k indicates thenumber of the binary auxiliary read values, where l indicates the numberof the check bits.
 32. The circuitry according to claim 16, wherein thecode is a linear code with a generator matrix G=(l, P) and the coder isimplemented so that the check bits c=c₁, . . . , c_(l) are determinedaccording to the relationc=c ₁ , . . . ,c _(l)={LH[BT(x ₁ , . . . ,x _(n))],A ₁ , . . . ,A _(q)}·P=(y ₁ , . . . ,y _(k) ,A ₁ , . . . ,A _(ij))·P wherein G is a (k+q,k+q+l)-matrix, I is a (k+q) identity matrix and P is a (k+q, l)-paritymatrix when the address bits are used for error detection via the bitsA₁, . . . , A_(q) derived from the address bits a₁, . . . , a_(Q), wherek indicates the number of the binary auxiliary read values, where lindicates the number of the check bits, and where q indicates the numberof the bits A₁, . . . , A_(q) derived from the address bits a₁, . . . ,a_(Q).
 33. The circuitry according to claim 16, wherein the firstsubcircuit for the transformation of the input values x₁, . . . , x_(n)into the output values z₁, . . . , z_(m), z_(m+1), . . . , z_(M) is aseries connection of a sixth subcircuit for the transformation of theinput values x₁, . . . , x_(n) into k binary auxiliary write values y₁^(s), . . . , t_(k) ^(s) and a seventh subcircuit for the transformationof the binary auxiliary write values y₁ ^(s), . . . , y_(k) ^(s) intothe output values z₁, . . . , z_(m), z_(m+1), . . . , z_(M) of the firstsubcircuit.
 34. The circuitry according to claim 33, wherein the sixthsubcircuit is implemented so that the auxiliary write values y₁ ^(s), .. . , y_(k) ^(s) determined by the sixth subcircuit are equal to theerror-free auxiliary read values y₁, . . . , y_(k) determined by thesecond subcircuit and the third subcircuit, and the encoder isimplemented so that it determines the check bits c₁, . . . , c_(l) usingthe auxiliary write values output by the sixth subcircuit.
 35. Thecircuitry according to claim 31, wherein the encoder is implemented sothat the check bits c=c₁, . . . , c_(l) are determined according to therelationc=c ₁ , . . . ,c _(l)=BBS(x ₁ , . . . ,x _(n))·P=(y ₁ ^(s) , . . . ,y_(k) ^(s))·P, wherein P is the (k, l)-parity matrix of theerror-correcting code.
 36. The circuitry according to claim 32, whereinthe encoder is configured so that the check bits c=c₁, . . . , c_(l) aredetermined according to the relationc=c ₁ , . . . ,c _(l)={BBS(x ₁ , . . . ,x _(n)),A ₁ , . . . ,A _(q)}·P=(y ₁ ^(s) , . . . ,y _(k) ^(s) ,A ₁ , . . . ,A _(q))·P wherein P isa (k+q, l)-parity matrix when the address bits are utilized for errordetection via the bits A₁, . . . , A_(q) derived from the address bitsa₁, . . . , a_(Q).
 37. The circuitry according to claim 16, wherein thesecond subcircuit for determining binary auxiliary read values y₁′, . .. , y_(k)′=LH(z₁′, . . . , z_(M)′) from the state values z₁′, . . . ,z_(M)′ read out from the memory is configured so that component-wise toeach ternary state component z_(i)′, i=1, . . . , m at least two binaryauxiliary read values are assigned and to each binary state componentz_(m+1), . . . , z_(M) at least one binary auxiliary read value isassigned, and so that k≧m+M applies.
 38. Circuitry for storing binarydata x₁, . . . , x_(n) and for error correction with a binary code,wherein the circuitry comprises: a ternary memory circuitry comprising aternary memory with ternary memory cells, wherein the ternary memorycircuitry is configured such that binary data x₁, . . . , x_(n) iswritable as encoded ternary states z₁, . . . , z_(M) at a write addressa₁, . . . , a_(Q) in one or more first memory cells of the memory cellsof the ternary memory, wherein the first memory cells of the memorycells of the ternary memory are configured to take on one of threedifferent states; a coder configured to write binary check bits c₁, . .. , c_(l) in second memory cells of the memory cells of the ternarymemory, wherein the coder is configured to write the binary check bitsc₁, . . . , c_(l) at a write address a₁, . . . , a_(Q) associated withthe data bits x₁, . . . , x_(n), when the binary check bits c₁, . . . ,c_(l) are check bits of the data bits x₁, . . . , x_(n), and when thedata bits x₁, . . . , x_(n) are written at the write address a₁, . . . ,a_(Q), wherein the ternary memory circuitry is configured to output,when reading at a read address a₁′, . . . , a_(Q) of memory cells of theternary memory, the memory cells configured to take on three differentvalues, state values z₁′, . . . , z_(M)′ and transform the state valuesz₁′, . . . , z_(M)′ into binary auxiliary read values y₁′, . . . ,y_(k)′, which are erroneous or not erroneous, and wherein the ternarymemory circuitry is configured to output, when reading at a read addressa₁′, . . . , a_(Q)′ of memory cells of the ternary memory, check bitsc₁′, . . . , c_(l)′, which are erroneous or not erroneous, and whereinthe ternary memory circuitry is configured to output, when the writeaddress is equal to the read address and when no error is present,error-free auxiliary read values y₁, . . . , y_(k) and error-free checkbits c₁, . . . , c_(l), wherein coder comprises a first n-bit wide firstinput for input of data bits x₁, . . . , x_(n) and a further q-bit wideinput for input of bits A₁, . . . , A_(q) and an l-bit wide output foroutput of check bits c₁, . . . , c_(l) wherein the bits A₁, . . . ,A_(q) depend on the bits of the write address a₁, . . . , a_(Q), whereinthe data bits x₁, . . . , x_(n), and the corresponding check bits arewritten to the write address a₁, . . . , a_(Q), and wherein the coder isconfigured such that the check bits c₁, . . . , c_(l) are determinedfrom the data bits x₁, . . . , x_(n) and the bits A₁, . . . , A_(q), sothaty ₁ , . . . ,y _(k) , A ₁ , . . . ,A _(q) , c ₁ , . . . ,c _(l) is acodeword of the error-correcting code, and wherein the bits A₁, . . . ,A_(q) are uniquely determined from the bits of the write address a₁, . .. , a_(Q), so that the bits A₁, . . . , A_(q) are output values of acombinational circuitry with Q binary inputs and q binary outputs, whenthe write address a₁, . . . , a_(Q) is fed into the inputs of saidcircuitry, wherein q≦Q applies.
 39. The circuitry according to claim 38,wherein q=Q, and wherein a₁, . . . , a_(Q)=A₁, . . . , A_(Q).
 40. Thecircuitry according to claim 38, wherein A₁=a₁⊕ . . . ⊕a_(Q).
 41. Thecircuitry according to claim 38, wherein the code is a linear code. 42.The circuitry according to claim 39, wherein the code is a linear code.43. The circuitry according to claim 40, wherein the code is a linearcode.
 44. The circuitry according to claim 38, wherein the code is alinear code with a generator matrix G=(l, P), and wherein l is a(k+q)-identity matrix, and wherein P is a [(k+q), l]-parity matrix, andwherein the check bits c₁, . . . , c_(l) are defined byc ₁ , . . . ,c _(l)=(y ₁ , . . . ,y _(k) ,A _(a) , . . . ,A _(Q))·P. 45.A method, comprising: generating a plurality of output values based on asequence of binary values, wherein each of the plurality of outputvalues has one of at least three different basic values; storing each ofthe output values as a state value in a different one of one or morememory cells of a plurality of memory cells of a memory, wherein the oneor more memory cells, in which the output values are stored, are eachconfigured to take on one of at least three different states; readingone or more of the state values from at least one of the memory cellswhich are configured to take on one of the at least three differentstates, wherein each of the one or more state values has one of at theat least three different basic values, wherein the binary auxiliary readvalues are determined based on the one or more state values; generatingone or more binary check bits so that the binary auxiliary read valuesand the one or more binary check bits together form one of the codewordsof the error-correcting code, when the binary auxiliary read values y₁′,. . . , y_(k)′ and the one or more binary check bits c₁, . . . , c_(l)are error-free; and storing each of the generated one or more check bitsin one or more of the memory cells of the memory, such that each of theone or more check bits is stored in a different one of the memory cellsof the memory, wherein each one of the memory cells in which a check bitis stored is configured to take on one of at least two different states.